F-Tile HDMI Intel® FPGA IP Design Example User Guide

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ID 709314
Date 8/05/2022
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup 3.10. Debugging Features
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer(Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = ON) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System 3.8.2. HDMI RX PHY 3.8.3. HDMI TX PHY 3.8.4. RX-TX Link
3.9. Hardware Setup x
3.9.1. Support additional video resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

3.8.2. HDMI RX PHY

Signal Direction Width Description
reset input 1 Reset to HDMI RX PHY module
sys_init output 1 A reset pulse to the HDMI RX PHY module upon power-up
device_ready input 1 Indicates the device is ready and reconfiguration process can begin
mgmt_clk input 1 Management clock. This clock is 100 Mhz frequency
i2c_clk input 1 Clock input for DDC and SCDC interface. The clock frequency is 100 Mhz.
systempll_clk input 1 Clock input for RX PHY System PLL clock
rx_phy_cdr_refclk input 1 Reference clock for CDR for use of FRL mode. The clock frequency is 100 Mhz
rx_phy_cdr_refclk_tmds input 1 Reference clock for CDR for use of TMDS mode. This clock is connected to the RX TMDS clock
rx_tmds_clk input 1 RX TMDS clock routed to the core for the reconfiguration module to measure the TMDS clock frequency to determine the incoming video pixel rate
hdmi_rx_serial_data input 4 HDMI RX clock, red, green, and blue serial data channels
hdmi_rx_serial_data_n input 4
hdmi_5v_detect_n input 1 HDMI 5 V detect signal from the HDMI sink connector
hdmi_rx_hpd output 1 HDMI hotplug detect signal from the HDMI sink connector
rx_vid_clk_in input 1 RX video clock input
rx_vid_clk output 1 RX video clock output
rx_vid_clk_locked input 1 Indicates RX video clock is stable
rx_pll_frl_locked output 1 Indicates IOPLL that generate the RX FRL clock is locked
rx_edid_ram_access input 1

Assert this port when you want to write or read from the EDID RAM, else this signal should be kept low.

When you assert this port, the hotplug signal deasserts to allow write or read to the EDID RAM. Once you have completed EDID RAM access, deassert this port and the hotplug signal asserts. The external HDMI source reads the new EDID due to the hotplug signal toggling

rx_tmds_freq output 24 Pixel clock frequency measured by reconfiguration module
rx_tmds_freq_valid output 1 Indicates rx_tmds_freq is valid
rx_phy_ready output 1 Indicates the RX PMA Direct PHY is ready
rx_hpd_trigger input 1 Assert this port for the HDMI RX core to toggle RX hotplug signal
rx_frl_clk output 1 Clock to RX FRL path
rx_phy_clk output 4 RX transceiver recovered clock
rx_os output 1

HDMI RX core data, status, and control ports.

Refer to Sink Interfaces section in HDMI Intel FPGA IP Core User Guide for more information
rx_parallel_data output 160
rx_core_in_lock output 1
rx_hpd_req input 1
rx_5v_detect output 1
rx_align_lock input 1
rx_core_locked output 1
rx_tbcr input 1
rx_frl_locked input 4
rx_frl_rate input 4
rx_rcfg_master_write output 1 RX reconfiguration Avalon Memory-mapped, control, and status interface to transceiver arbiter
rx_rcfg_master_read output 1
rx_rcfg_master_address output 10
rx_rcfg_master_writedata output 32
rx_rcfg_master_readdata input 32
rx_rcfg_master_waitrequest input 1
rx_rcfg_master_new_cfg_applied input 1
rx_rcfg_master_readdata_valid input 1
rx_rcfg_master_new_cfg_applied_ack output 1
rx_rcfg_curr_profile_id input 15
rx_rcfg_busy output 1
rx_dr_id output 5
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