F-Tile JESD204C Intel® FPGA IP User Guide

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Date 4/26/2022
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

8.2. Receiver Registers

TX Register Map and Definition

Table 49.  Register Map for F-Tile JESD204C TX Registers
Address Description
0x0 Link Lane Control Common
0x4 Link Lane Control 0
0x8 Link Lane Control 1
0xC Link Lane Control 2
0x10 Link Lane Control 3
0x14 Link Lane Control 4
0x18 Link Lane Control 5
0x1C Link Lane Control 6
0x20 Link Lane Control 7
0x24 Link Lane Control 8
0x28 Link Lane Control 9
0x2C Link Lane Control 10
0x30 Link Lane Control 11
0x34 Link Lane Control 12
0x38 Link Lane Control 13
0x3C Link Lane Control 14
0x40 Link Lane Control 15
0x44 – 0x4F N/A
0x50 Transport Layer Control
0x54 SYSREF Control
0x58 – 0x5F N/A
0x60 JESD204 RX Error
0x64 JESD204 RX Error Interrupt Enable
0x68 JESD204 RX Error Link Reinit Enable
0x6C – 0x7F N/A
0x80 JESD204 RX Status 0
0x84 – 0x8c N/A
0x8C JESD204 RX Status 3
0x90 JESD204 RX Status 4
0x94 JESD204 RX Status 5
0x98 JESD204 RX Status 6
0x9C JESD204 RX Status 7
0xA0 – 0xBC N/A
0xC0 JESD204 RX Converter Parameter 1
0xC4 JESD204 RX Converter Parameter 2
0xC8 – 0x3F8 N/A
0x3FC Unused
Note: When you turn on Enable CSR optimization, all Avalon® memory-mapped access to all CSR is lost.
Table 50.  lane_ctrl_commonCommon lane control and assignment. The common lane control applies to all lanes in the link.

Offset: 0x0

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:11 Reserved Reserved RV 0x0
10 rx_2b_lben Enables the 66 bit interface loopback from TX. Instead of taking RX gearbox data, TX loopback data is multiplexed in for subsequent RX operation. RW 0x0
9:6 rx_thresh_sh_err The number of consecutive erroneous sequences required to force the algorithm back to initial SH_INIT. 0-based value. 0=threshold of 1. ‘d15= threshold of 16. RW Compile-time specific
5:3 rx_thresh_emb_err The number of consecutive erroneous sequences required to force the algorithm back to initial EMB_INIT. 0-based value. 0=threshold of 1. ‘d7= threshold of 8. RW Compile-time specific
2:1 Reserved Reserved RV 0x0
0 bit_reversal

This is a compile-time option which needs to be set before IP generation.

  • 0 = LSB-first serialization
  • 1 = MSB-first serialization
Note: The F-Tile JESD204C converter device may support either MSB-first serialization or LSB-first serialization.

When bit_reversal = 1, the word aligner reverses RX parallel data bits upon receiving the PMA deserialized data. For example; in 64-bit mode => D[63:0] is rewired to D[0:63]

RO 0x0
Table 51.  lane_ctrl_0Lane control and assignment for Lane 0.

Offset: 0x4
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 52.  lane_ctrl_1Lane control and assignment for Lane 1.

Offset: 0x8
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 53.  lane_ctrl_2Lane control and assignment for Lane 2.

Offset: 0xC
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 54.  lane_ctrl_3Lane control and assignment for Lane 3.

Offset: 0x10
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 55.  lane_ctrl_4Lane control and assignment for Lane 4.

Offset: 0x14
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 56.  lane_ctrl_5Lane control and assignment for Lane 5.

Offset: 0x18
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 57.  lane_ctrl_6Lane control and assignment for Lane 6.

Offset: 0x1C
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 58.  lane_ctrl_7Lane control and assignment for Lane 7.

Offset: 0x20
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 59.  lane_ctrl_8Lane control and assignment for Lane 8.

Offset: 0x24
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 60.  lane_ctrl_9Lane control and assignment for Lane 9.

Offset: 0x28
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 61.  lane_ctrl_10Lane control and assignment for Lane 10.

Offset: 0x2C
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 62.  lane_ctrl_11Lane control and assignment for Lane 11.

Offset: 0x30
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 63.  lane_ctrl_12Lane control and assignment for Lane 12.

Offset: 0x34
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 64.  lane_ctrl_13Lane control and assignment for Lane 13.

Offset: 0x38
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 65.  lane_ctrl_14Lane control and assignment for Lane 14.

Offset: 0x3C
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 66.  lane_ctrl_15Lane control and assignment for Lane 15.

Offset: 0x40
Bit Name Description Attribute Reset
31:1 Reserved Reserved RV 0x0
0 lane_polarity_en

Set 1 to enable lane polarity detection.

When set, the RX interface detects and inverts the polarity of the RX data.

If you turn on Enable CSR optimization and Lane Polarity Attribute, this register is RO. Otherwise, it is RW.

RW/RO POL_ENx
Table 67.  tl_ctrlTransport layer control.

Offset: 0x50

Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2:1 width_mult

This is a compile-time option which needs to be set before IP generation.

Total Sample width multiplier

2’b00: Width equals to M*N*S

2’b01: Width equals to 2*M*N*S

2’b10: Width equals to 4*M*N*S

2’b11: Width equals to 8*M*N*S

 RO Compile-time specific
0 fclk_mult

This is a compile-time option which needs to be set before IP generation.

Frame clock multiplier

0: Frame clock frequency is the same as link clock frequency.

1: Frame clock frequency is two times the link clock frequency.

RO Compile-time specific
Table 68.  sysref_ctrlSYSREF control.

Offset: 0x54

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:27 Reserved Reserved RV 0x0
26 force_rbd_release Setting this bit will force RBD elastic buffer to be released immediately when the latest arrival lane arrived in the system. It indirectly forces rbd_offset == rx_status0 (0x80) rbd_count. This register overrides rbd_offset. RW Compile-time specific
25:16 rbd_offset RX Buffer Delay (RBD) offset. RX elastic buffer will align the data from multiple lanes of the link and release the buffer at the LEMC boundary (rbd_offset = 0).

This register provides flexibility for an early RBD release opportunity. Legal value of RBD offset is from (E*32-1) down to 0 as it is aligned in number of link clocks. If rbd_offset is set out of the legal value, the RBD elastic buffer will be immediately released.

(E*32) refers to 64 bit design.

 RW Compile-time specific
15:8 lemc_offset

Upon the detection of the rising edge of SYSREF in continuous mode or single detect mode, the LEMC counter will be reset to the value set in lemc_offset. LEMC counter operates in the link clock domain, therefore the legal value for the counter is from 0 to (E*32)-1.

  • In the event that (E*32)-1 > 255, the design has no capability to adjust the LEMC for offset greater than 255.
  • If (E*32)-1 < 255, and an out-of-range value is set, the LEMC offset will be internally reset to 0.

By default, the rising edge of SYSREF resets the LEMC counter to 0. However, if the system design has a large phase offset between the SYSREF sampled by the converter device and the FPGA, you can virtually shift the SYSREF edges by changing the LEMC offset reset value using this register.

If you turn on Enable CSR optimization, this bit cannot be cleared by hardware. Hence the LEMC counter always resets to the new SYSREF edge.

RW Compile-time specific
7:3 Reserved Reserved RV 0x0
2 sysref_singledet

This register enables LEMC realignment with a single sample of the rising edge of SYSREF. The bit is auto-cleared by hardware once SYSREF is sampled. If the user requires SYSREF to be sampled again (due to link reset or reinitialization), you must set this bit again.

This register also has another critical function: The F-Tile JESD204C IP will never send EoEMB unless at least a SYSREF edge is sampled. This is to prevent race condition between SYSREF being sampled at TX (logic device) and the deterministic timing of EoEMB transmission.

  • 0 = Any rising edge of SYSREF will not reset the LEMC counter.
  • SYSREF and then clears this bit. (Default)

Intel recommends to use 1 = Resets the LEMC counter on the first rising edge of sysref_singledet with sysref_alwayson even if you want to do SYSREF continuous detection mode. This is because this register is able to indicate whether SYSREF was ever sampled. This register also prevents race condition as mentioned above. Using only SYSREF single detect mode will not be able to detect incorrect SYSREF period.

If you turn on Enable CSR optimization, this bit cannot be cleared by hardware. Hence the LEMC counter always resets to the new SYSREF edge.

RW1S 0x1
1 sysref_alwayson

This register enables LEMC realignment at every rising edge of SYSREF. LEMC counter is reset when every SYSREF transition from 0 to 1 is detected.

0 = Any rising edge of SYSREF will not reset the LEMC counter.

1 = Continuously resets LEMC counter at every SYSREF rising edge.

When this bit is set, the SYSREF period will be checked to make sure it never violates internal extended multiblock period and this period can only be n-integer multiplied of (E*32).

Note: When this bit is set, the SYSREF period will be checked to make sure it never violates internal extended multiblock period and this period can only be n-integer multiplied of (E*32). If the SYSREF period s different from the local extended multiblock period, the sysref_lemc_err (0x60) register will be asserted and an interrupt will be triggered.

If you want to change the SYSREF period, this bit should be set to 0 first. After SYSREF clock has stabilized, this bit is set to 1 to sample the rising edges of the new SYSREF.

RW 0x0
0 link_reinit

The F-Tile JESD204C IP reinitializes the RX link by resetting all internal pipestages and status, but not including SYSREF detection information.

(This bit will automatically be cleared once link reinitialization is entered by hardware).

  • 0 = No link reinit request (Default)
  • 1 = Reinitialize the link.
 RW1S 0x0
Table 69.  rx_errThis register logs errors detected in the FPGA IP. Each set bit in the register will generate interrupt, if enabled by corresponding bits in the RX Error Enable register( rx_err_enable (0x64)). After servicing the interrupt, software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending.

Offset: 0x60
Bit Name Description Attribute Reset
31:23 Reserved Reserved RV 0x0
22 ecc_fatal_err Assert when ECC fatal error occurs. This reflects a double bit error detected and uncorrected. RW1C 0x0
21 ecc_corrected_err Assert when ECC error has been corrected. This reflects a single bit error detected and corrected. RW1C 0x0
20 eb_full_err Assert when any of the RX elastic buffer detected an overflow condition. RW1C 0x0
19 emb_unlock_err Assert when any of the extended multiblock alignment logic detected an “unlock” due to error count> error threshold. RW1C 0x0
18 sh_unlock_err Assert when any of sync header alignment logic detected an “unlock” due to error count> error threshold. RW1C 0x0
17 rx_gb_overflow_err Assert when overflow happens on any of the lane’s RX gearbox. RW1C 0x0
16 rx_gb_underflow_err Assert when underflow happens on any of the lane’s RX gearbox. RW1C 0x0
15 Reserved Reserved RV 0x0
14 crc_err The RX CRC generator has calculated a parity that does not match the parity received in the sync word. RW1C 0x0
13 Reserved Reserved RV 0x0
12 Reserved Reserved RV 0x0
11 cmd_par_err The final parity bit in the command channel data for a given sync word does not match the calculated parity for the received command channel bits. RW1C 0x0
10 invalid_eoemb The EoEMB identifier in the pilot signal has an unexpected value. RW1C 0x0
9 invalid_eomb The “00001” sequence in the pilot signal is not received at an expected location in the sync word. RW1C 0x0
8 invalid_sync_header “11” or “00” received in expected sync header location RW1C 0x0
7 lane_deskew_err

Asserted when lane to lane deskew exceeds the LEMC boundary. This error will trigger when rbd_offset is not correctly programmed or the lane to lane skew within the device or across multidevice has exceeded the LEMC boundary.

EoEMB for all lanes should be within one LEMC boundary.

Refer to Deterministic Latency for more information.

RW1C 0x0
6 src_rx_alarm Detected rx_alarm signal assertion from the F-tile SRC. This event overlaps with pll_lock_err but SRC may add new events to the rx_alarm list. RW1C 0x0
5 syspll_lock_err Detected system PLL unlock when the F-Tile JESD204C link is running. RW1C 0x0
4 cdr_locked_err Detected 1 or more lanes of CDR locked lose lock when the F-Tile JESD204C link is running. RW1C 0x0
3 cmd_ready_err This error bit is applicable only if command channel is used in the F-Tile JESD204C link. This error bit asserts if the upstream component deasserts the j204c_rx_cmd_ready signal while the link layer is sending command (via j204c_rx_cmd_valid). RW1C 0x0
2 frame_data_ready_err

This error bit asserts if the RX detects data ready by the upstream component is 0 on the Avalon® streaming bus when the data is valid. The transport layer expects the upstream device in the system ( Avalon® streaming sink component) will always be ready to receive the valid data from the transport layer.

Note: If this error detection is not required, you can tie off the data ready signal from the upstream to 1, j204_rx_avst_ready in the transport layer.
RW1C 0x0
1 dll_data_ready_err

This error bit will be asserted if the RX detects data ready by the upstream component is 0 on the Avalon® streaming bus when data is valid. By design, the F-Tile JESD204C RX IP core expects the upstream device (F-Tile JESD204C transport layer/application layer) will always be ready to receive the valid data from the F-Tile JESD204C RX IP.

Note: If this error detection is not required, you can tie off the Avalon® streaming j204_rx_avst_ready signal to 1.
RW1C 0x0
0 sysref_lemc_err When the sysref_alwayson (0x54) register is set to 1, the LEMC counter checks whether the SYSREF period matches the LEMC counter where it is n-integer multiplier of the (E*32).

If the SYSREF period does not match the LEMC period, the IP asserts this bit.

RW1C 0x0
Note: When you turn on Enable CSR optimization, all error reporting through this CSR is lost.
Table 70.  rx_err_enThis register enables the error types that will generate interrupt. Setting 0 to the register bits will disable the specific error type from generating interrupt.

Offset: 0x64
Bit Name Description Attribute Reset
31:23 Reserved Reserved RV 0x0
22 ecc_fatal_err_en ECC fatal error interrupt enable RW 0x1
21 ecc_corrected_err_en ECC corrected error interrupt enable RW 0x0
20 eb_full_err_en Elastic buffer full error interrupt enable RW 0x1
19 emb_unlock_err_en EMB alignment unlock error interrupt enable RW 0x1
18 sh_unlock_err_en Sync header alignment unlock error interrupt enable RW 0x1
17 rx_gb_overflow_err_en Gearbox overflow error interrupt enable RW 0x1
16 rx_gb_underflow_err_en Gearbox underflow error interrupt enable RW 0x1
15 Reserved Reserved RV 0x0
14 crc_err_en CRC error interrupt enable RW 0x1
13 Reserved Reserved RV 0x0
12 Reserved Reserved RV 0x0
11 cmd_par_err_en Command parity error interrupt enable RW 0x1
10 invalid_eoemb_en Invalid EoEMB error interrupt enable RW 0x1
9 invalid_eomb_en Invalid EoMB error interrupt enable RW 0x1
8 invalid_sync_header_en Invalid sync header error interrupt enable RW 0x1
7 lane_deskew_err_en Lane deskew error interrupt enable RW 0x1
6 src_rx_alarm_en SRC RX alarm interrupt enable RW 0x1
5 syspll_lock_err_en System PLL lock error interrupt enable RW 0x1
4 gb_under CDR lost lock error interrupt enable RW 0x1
3 cmd_ready_err_en Command data ready error interrupt enable RW 0x0
2 frame_data_ready_err_en Frame data ready error interrupt enable RW 0x0
1 dll_data_ready_err_en Link data ready error interrupt enable RW 0x0
0 sysref_lemc_err_en SYSREF LEMC error interrupt enable RW 0x1
Note: When you turn on Enable CSR optimization, the RX IP will not trigger any interrupt for errors.
Table 71.  rx_err_link_reinitThis register enables the error types that will generate link reinitialization. Setting 0 to the register bits will disable the specific error type from link reinitialization.

Offset: 0x68
Bit Name Description Attribute Reset
31:23 Reserved Reserved RV 0x0
22 ecc_fatal_err_en_reinit ECC fatal error reinitialization enable RW 0x0
21 ecc_corrected_err_en_reinit ECC corrected error reinitialization enable RW 0x0
20 eb_full_err_en_reinit Elastic buffer full error reinitialization enable RW 0x0
19 Reserved Reserved RV 0x0
18 Reserved Reserved RV 0x0
17 Reserved Reserved RV 0x0
16 Reserved Reserved RV 0x0
15 Reserved Reserved RV 0x0
14 crc_err_en_reinit CRC error reinitialization enable RW 0x0
13 Reserved Reserved RV 0x0
12 Reserved Reserved RV 0x0
11 cmd_par_err_en_reinit Command parity error reinitialization enable RW 0x0
10 invalid_eoemb_en_reinit Invalid EoEMB error reinitialization enable RW 0x0
9 invalid_eomb_en_reinit Invalid EoMB error reinitialization enable RW 0x0
8 invalid_sync_header_en_reinit Invalid sync header error reinitialization enable RW 0x0
7 lane_deskew_err_en_reinit Lane deskew error reinitialization enable RW 0x0
6 Reserved Reserved RV 0x0
5 Reserved Reserved RV 0x0
4 Reserved Reserved RV 0x0
3 cmd_ready_err_en_reinit Command data ready error reinitialization enable RW 0x0
2 frame_data_ready_err_en_reinit Frame data ready error reinitialization enable RW 0x0
1 dll_data_ready_err_en_reinit Link data ready error reinitialization enable RW 0x0
0 sysref_lemc_err_en_reinit SYSREF LEMC error reinitialization enable RW 0x0
Note: When you turn on Enable CSR optimization, the RX IP will not trigger any reinitialization due to errors enabled in this register.
Table 72.  rx_status0Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x80

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:24 Reserved Reserved RV 0x0
23 sysref_det_pending Indicate that sysref is yet to be detected. sysref_ctrl.sysref_singledet needs to be set to enable link initialization. ROV 0x0
22 reinit_in_prog Indicates that auto or manual link reinitialization is in progress. ROV 0x0
21:12 rbd_count_early
  • When rbd_count_early = 0, this indicates that the earliest lane arrives within the link at the LEMC boundary.
  • When rbd_count_early = 1, this indicates that the earliest lane arrives within the link at 1 link clock cycle after the LEMC boundary.
ROV 0x0
11:2 rbd_count

Legal value reported from this register is 0 to 1023. When rbd_count = 0, this indicates that the latest lane arrives within the link at the LEMC boundary. When rbd_count = 1, this indicates that the latest lane arrives within the link at 1 link clock cycle after the LEMC boundary.

Note: When the latest lane arrival in the link is too close to the LEMC boundary, Intel recommends you set the RBD release opportunity (rbd_offset) at least 2 link clocks away from rbd_count to accommodate for worst-case power cycle variation.

Refer to Deterministic Latency for more information.

ROV 0x0
1:0 sh_config

b00: CRC-12

b01: Standalone command channel

b10: Reserved (CRC-3)

 RO Compile-time specific
Table 73.  rx_status3Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x8C
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15 lane15_rx_cdr_locked RX CDR lock status flag for Lane 15 ROV 0x0
14 lane14_rx_cdr_locked RX CDR lock status flag for Lane 14 ROV 0x0
13 lane13_rx_cdr_locked RX CDR lock status flag for Lane 13 ROV 0x0
12 lane12_rx_cdr_locked RX CDR lock status flag for Lane 12 ROV 0x0
11 lane11_rx_cdr_locked RX CDR lock status flag for Lane 11 ROV 0x0
10 lane10_rx_cdr_locked RX CDR lock status flag for Lane 10 ROV 0x0
9 lane9_rx_cdr_locked RX CDR lock status flag for Lane 9 ROV 0x0
8 lane8_rx_cdr_locked RX CDR lock status flag for Lane 8 ROV 0x0
7 lane7_rx_cdr_locked RX CDR lock status flag for Lane 7 ROV 0x0
6 lane6_rx_cdr_locked RX CDR lock status flag for Lane 6 ROV 0x0
5 lane5_rx_cdr_locked RX CDR lock status flag for Lane 5 ROV 0x0
4 lane4_rx_cdr_locked RX CDR lock status flag for Lane 4 ROV 0x0
3 lane3_rx_cdr_locked RX CDR lock status flag for Lane 3 ROV 0x0
2 lane2_rx_cdr_locked RX CDR lock status flag for Lane 2 ROV 0x0
1 lane1_rx_cdr_locked RX CDR lock status flag for Lane 1 ROV 0x0
0 lane0_rx_cdr_locked RX CDR lock status flag for Lane 0 ROV 0x0
Table 74.  rx_status4Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x90
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15 lane15_sh_lock RX sync header alignment lock status flag for Lane 15 ROV 0x0
14 lane14_sh_lock RX sync header alignment lock status flag for Lane 14 ROV 0x0
13 lane13_sh_lock RX Sync Header alignment lock status flag for Lane 13 ROV 0x0
12 lane12_sh_lock RX sync header alignment lock status flag for Lane 12 ROV 0x0
11 lane11_sh_lock RX sync header alignment lock status flag for Lane 11 ROV 0x0
10 lane10_sh_lock RX sync header alignment lock status flag for Lane 10 ROV 0x0
9 lane9_sh_lock RX sync header alignment lock status flag for Lane 9 ROV 0x0
8 lane8_sh_lock RX sync header alignment lock status flag for Lane 8 ROV 0x0
7 lane7_sh_lock RX sync header alignment lock status flag for Lane 7 ROV 0x0
6 lane6_sh_lock RX sync header alignment lock status flag for Lane 6 ROV 0x0
5 lane5_sh_lock RX sync header alignment lock status flag for Lane 5 ROV 0x0
4 lane4_sh_lock RX sync header alignment lock status flag for Lane 4 ROV 0x0
3 lane3_sh_lock RX sync header alignment lock status flag for Lane 3 ROV 0x0
2 lane2_sh_lock RX sync header alignment lock status flag for Lane 2 ROV 0x0
1 lane1_sh_lock RX sync header alignment lock status flag for Lane 1 ROV 0x0
0 lane0_sh_lock RX sync header alignment lock status flag for Lane 0 ROV 0x0
Table 75.  rx_status5Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x94
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15 lane15_emb_lock RX EMB alignment lock status flag for Lane 15 ROV 0x0
14 lane14_emb_lock RX EMB alignment lock status flag for Lane 14 ROV 0x0
13 lane13_emb_lock RX EMB alignment lock status flag for Lane 13 ROV 0x0
12 lane12_emb_lock RX EMB alignment lock status flag for Lane 12 ROV 0x0
11 lane11_emb_lock RX EMB alignment lock status flag for Lane 11 ROV 0x0
10 lane10_emb_lock RX EMB alignment lock status flag for Lane 10 ROV 0x0
9 lane9_emb_lock RX EMB alignment lock status flag for Lane 9 ROV 0x0
8 lane8_emb_lock RX EMB alignment lock status flag for Lane 8 ROV 0x0
7 lane7_emb_lock RX EMB alignment lock status flag for Lane 7 ROV 0x0
6 lane6_emb_lock RX EMB alignment lock status flag for Lane 6 ROV 0x0
5 lane5_emb_lock RX EMB alignment lock status flag for Lane 5 ROV 0x0
4 lane4_emb_lock RX EMB alignment lock status flag for Lane 4 ROV 0x0
3 lane3_emb_lock RX EMB alignment lock status flag for Lane 3 ROV 0x0
2 lane2_emb_lock RX EMB alignment lock status flag for Lane 2 ROV 0x0
1 lane1_emb_lock RX EMB alignment lock status flag for Lane 1 ROV 0x0
0 lane0_emb_lock RX EMB alignment lock status flag for Lane 0 ROV 0x0
Table 76.  rx_status6Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x98
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15 lane15_rx_eb_full RX Elastic buffer full status flag for Lane 15 ROV 0x0
14 lane14_rx_eb_full RX Elastic buffer full status flag for Lane 14 ROV 0x0
13 lane13_rx_eb_full RX Elastic buffer full status flag for Lane 13 ROV 0x0
12 lane12_rx_eb_full RX Elastic buffer full status flag for Lane 12 ROV 0x0
11 lane11_rx_eb_full RX Elastic buffer full status flag for Lane 11 ROV 0x0
10 lane10_rx_eb_full RX Elastic buffer full status flag for Lane 10 ROV 0x0
9 lane9_rx_eb_full RX Elastic buffer full status flag for Lane 9 ROV 0x0
8 lane8_rx_eb_full RX Elastic buffer full status flag for Lane 8 ROV 0x0
7 lane7_rx_eb_full RX Elastic buffer full status flag for Lane 7 ROV 0x0
6 lane6_rx_eb_full RX Elastic buffer full status flag for Lane 6 ROV 0x0
5 lane5_rx_eb_full RX Elastic buffer full status flag for Lane 5 ROV 0x0
4 lane4_rx_eb_full RX Elastic buffer full status flag for Lane 4 ROV 0x0
3 lane3_rx_eb_full RX Elastic buffer full status flag for Lane 3 ROV 0x0
2 lane2_rx_eb_full RX Elastic buffer full status flag for Lane 2 ROV 0x0
1 lane1_rx_eb_full RX Elastic buffer full status flag for Lane 1 ROV 0x0
0 lane0_rx_eb_full RX Elastic buffer full status flag for Lane 0 ROV 0x0
Table 77.  rx_status7Monitor ports of internal signals and counter which will be useful for debugging.

Offset: 0x9C
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15 lane15_rx_polarity RX polarity inversion status flag for Lane 15 ROV 0x0
14 lane14_rx_polarity RX polarity inversion status flag for Lane 14 ROV 0x0
13 lane13_rx_polarity RX polarity inversion status flag for Lane 13 ROV 0x0
12 lane12_rx_polarity RX polarity inversion status flag for Lane 12 ROV 0x0
11 lane11_rx_polarity RX polarity inversion status flag for Lane 11 ROV 0x0
10 lane10_rx_polarity RX polarity inversion status flag for Lane 10 ROV 0x0
9 lane9_rx_polarity RX polarity inversion status flag for Lane 9 ROV 0x0
8 lane8_rx_polarity RX polarity inversion status flag for Lane 8 ROV 0x0
7 lane7_rx_polarity RX polarity inversion status flag for Lane 7 ROV 0x0
6 lane6_rx_polarity RX polarity inversion status flag for Lane 6 ROV 0x0
5 lane5_rx_polarity RX polarity inversion status flag for Lane 5 ROV 0x0
4 lane4_rx_polarity RX polarity inversion status flag for Lane 4 ROV 0x0
3 lane3_rx_polarity RX polarity inversion status flag for Lane 3 ROV 0x0
2 lane2_rx_polarity RX polarity inversion status flag for Lane 2 ROV 0x0
1 lane1_rx_polarity RX polarity inversion status flag for Lane 1 ROV 0x0
0 lane0_rx_polarity RX polarity inversion status flag for Lane 0 ROV 0x0
Table 78.  rx_converter_param1Link and transport control configuration per converter parameters.

Offset: 0xC0

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:30 CS Number of control bits per converter sample. 1-based value. For example, 0=0 bit, 1=1 bit. RO Compile-time specific
29 HD High Density format. RO Compile-time specific
28:24 N

Number of data bits per converter sample. 0-based value. For example, 0=0 bit, 1=2 bits.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
23:16 M

Number of converters per device. 0-based value. For example, 0=1 converter, 1=2 converters.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
15:8 F

Number of octets per frame per lane. 0-based value. For example, 0=1 octet, 1=2 octets.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
7:4 Reserved Reserved RV 0x0
3:0 L

Number of lanes per link. 0-based value. For example, 0=1 lane, 1=2 lanes.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
Table 79.  rx_converter_param2Link and Transport control configuration per converter parameters.

Offset: 0xC4

Note: For bits that are compile-time specific, you must recompile to change the reset value.
Bit Name Description Attribute Reset
31:24 E

Number of multiblock within an extended multiblock. 0-based value.For example, 0=1 multiblock to form extended multiblock, 1=2 multiblock to form an extended multiblock.

If (256 Mod F) =1, E must be greater than 1. (The register value should be greater than 0).

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7
RO Compile-time specific
23:21 Reserved Reserved RV 0x0
20:16 CF Number of control words per frame clock per link. 1-based value. For example, 0=0 word, 1=1 word. RO Compile-time specific
15:13 Reserved Reserved RO 0x0
12:8 S

Number of samples per converter frame cycle. 0-based value. For example, 0=1 sample, 1=2 samples.

Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
7:5 subclass_ver

Device Subclass Version

  • b000: Subclass 0
  • b001: Subclass 1
 RO Compile-time specific
4:0 NP
Number of data bits+control bits+tail bits per converter sample. 0-based value. For example, 0=1 bit, 1=2 bits.
Note: CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.
RO Compile-time specific
Level Two Title