F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 10/11/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

6. F-Tile JESD204C Intel® FPGA IP Parameters

Table 18.   F-Tile JESD204C Intel® FPGA IP Parameters
Parameter Value Description
Main Tab
Device family Intel® Agilex™ Supports Intel® Agilex™ F-Tile devices.
JESD204C wrapper
  • Both Base and PHY
 Supports a single wrapper.
  • Both Base and PHY—generates both the base (data link layer and transport layer) and the transceiver PHY layer (hard PMA).
Data path
  • Receiver
  • Transmitter
  • Duplex
 Select the operation modes. This selection enables or disables the receiver and transmitter supporting logic.
  • Receiver—instantiates the receiver to interface to the ADC.
  • Transmitter—instantiates the transmitter to interface to the DAC.
  • Duplex—instantiates the receiver and transmitter to interface to both the ADC and DAC.

JESD204C Subclass

  • 0
  • 1
 Select the F-Tile JESD204C subclass modes.
  • 0—Set subclass 0
  • 1—Set subclass 1

Data rate

5.0–32 Gbps Set the lane rate for each lane. The maximum rate is 32 Gbps. Refer to Performance and Resource Utilization for more information.

Transceiver type

F-tile Default option is F-tile.
Bonding mode
  • Bonded
  • Non-bonded
 Set the bonding modes.
  • Bonded—Select this option to minimize inter-lanes skew for the transmitter datapath.
  • Non-bonded—Select this option to disable inter-lanes skew control for the transmitter datapath.
Note: The IP automatically sets the bonding type based on the device family and number of lanes you set.

PLL/CDR reference clock frequency

Variable Set the transceiver reference clock frequency for PLL and/or CDR. The frequency range available for you to choose depends on the data rate.
System PLL frequency Variable Specify the System PLL clock frequency used in the Tile.
Note: For Intel® Agilex™ devices with F- transceiver tiles, the system PLL is outside of F-Tile JESD204C Intel® FPGA IP. Use this option to set the system PLL clock frequencies in the generated SDC constraint file. This setting does not directly affect the frequency of the system PLL.
Enable dynamic reconfiguration On, Off Enable the dynamic data rate change to the PMA. The default value is On.
JESD204C Configurations Tab

Lanes per converter device (L)

1–16 Set the number of lanes per converter device.

Converters per device (M)

1–32 Set the number of converters per converter device.

Octets per frame (F)

1–256 The number of octets per frame is derived from F= M*N'*S/(8*L).

Converter resolution (N)

1–32 Set the number of conversion bits per converter.

Transmitted bits per sample (N')

4–32 Set the number of transmitted bits per sample (JESD204 word size, which is in nibble group).
Note: If parameter CF equals to 0 (no control word), parameter N' must be larger than or equal to sum of parameter N and parameter CS (N' ≥ N + CS). Otherwise, parameter N' must be larger than or equal to parameter N (N'≥N).

Samples per converter per frame (S)

1–32 Set the number of transmitted samples per converter per frame.

Multiblocks in an extended multiblock (E)

1–32 Set the number of multiblock within an extended multiblock.

Control bits (CS)

0–3 Set the number of control bits per conversion sample.

Control words (CF)

0–31 Set the number of control words per frame clock period per link.

High-density user data format (HD)

0–1 Turn on this option to set the data format. This parameter controls whether a sample may be divided over more lanes.
  • 1 (On)—High Density format
  • 0 (Off)—Data should not cross the lane boundary
Sync header configuration (SH_CONFIG)
  • CRC-12
  • Standalone command channels
 Set the sync header (SH) encoding configuration.
  • CRC-12—For the sync word to contain error detection information.
  • Standalone command channel—For the sync word to contain transmit commands and status information.
Frame clock frequency multiplier (FCLK_MULP) 1, 2 Select the frame clock frequency multiplier (FCLK). The default and recommended value is 1.
  • 1—Frame clock and link clock are at the same frequency.
  • 2—Frame clock frequency is two times the link clock frequency.
Frame data width multiplier (WIDTH_MULP) 1, 2, 4, 8 Select the data width multiplier between the application layer and transport layer.
Note: The multiplier value is auto-calculated based on the M, N, S, and F configurations. Select the smallest data width multiplier value on the list. Other data width multiplier values are not allowed.
Enable fabric to tile TX data pipestage (Transmitter) On, Off Enable pipeline stage in TX datapath to tile for timing improvement. Turning on requires additional resources.
  • Off—Do not insert any pipeline stage. Minimum latency.
  • On—Insert 1 pipeline stage.
Note: For high data rates, Intel recommends that you enable pipeline stages for better timing.
TX LEMC offset (Transmitter) 0–255 TX LEMC offset from SYSREF. The default value is 0.
EMB error threshold (Receiver) 1–8 EMB error threshold to unlock EMB FSM back to initialization state. The default value is 8.
SH error threshold (Receiver) 1–16 Sync header error threshold to unlock SH FSM back to initialization state. The default value is 16.
RX LEMC offset (Receiver) 0–255 RX LEMC offset from SYSREF. The default value is 0.
RBD offset (Receiver) 0–1023 Elastic buffer release point (reference to LEMC) for Subclass 1 usage. The default value is 0.

One full LEMC, N number means (LEMC – N) cycles to release data in elastic buffer when deskew alignment is achieved.

Enable ECC in M20K DCFIFO (Receiver) On, Off Turn on to enable ECC feature if M20K is used as FIFO.
Lane polarity attribute (Receiver)
  • Optimize away
  • Writable
 Select whether you want the lane polarity attribute to be read-only (RO) or read and write (RW).
  • Optimize away—Select this option to enable the attribute to be read-only.
  • Writable—Select this option to enable the attribute to be read and write.

Applies only for RX.
Enable lane polarity detection (Receiver) 16'h0–16'hFFFF Specify the bit representing the polarity enable status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 15, and so on.

This value depends on the number of lanes you specify.

Polarity inversion (Receiver) 16'h0–16'hFFFF Specify the bit representing the polarity inversion status of each lane. For example, LSB represents lane 0, LSB+1 represents lane 1, MSB represents lane 15, and so on.

This value depends on the number of lanes you specify.

Single lane mode (Receiver) On, Off Turn on only when you set the Sync header configuration parameter to Standalone command channel.
Configurations and Status Registers Tab

Enable CSR optimization

On, Off

Turn on to optimize the usage of the registers, including the Avalon® memory-mapped interfaces.

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