F-Tile JESD204C Intel® FPGA IP Design Example User Guide

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ID 691269
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide 2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the F-Tile JESD204C Design Example 4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Simulating the Design Example Testbench 2.5. Compiling the Design Example 2.6. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the F-Tile JESD204C Design Example x
3.1. System Components 3.2. F-Tile JESD204C Design Example Clock and Reset 3.3. F-Tile JESD204C Design Example Signals 3.4. F-Tile JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. IOPLL 3.1.5. SYSREF Generator 3.1.6. Reset Sequencers 3.1.7. 3-Wire SPI 3.1.8. System PLL 3.1.9. Pattern Generator and Checker 3.1.10. F-Tile JESD204C TX and RX IP
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the F-Tile JESD204C Intel® FPGA IP Design Example User Guide
2. F-Tile JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the F-Tile JESD204C Design Example
4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

4. Document Revision History for the F-Tile JESD204C Intel® FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.12.13 21.4 1.0.0
  • Added new topics:
    • Compiling and Testing the Design
    • Hardware Test for System Console Control Design Example
    • Board Connectivity
  • Updated topic title Software Requirements to Hardware and Software Requirements.
  • Updated Table: Parameters in the Example Design Tab to include the Agilex I-Series Transceiver-SoC Development Kit option under the Select board parameter.
  • Updated the list of files under the ed/rtl folder in Table: Directory Files.
  • Updated the descriptions of the following clock signals in Table: Design Example Clocks:
    • mgmt_rst_in_n
    • j204c_tx_rst_n
    • j204c_rx_rst_n
  • Updated the reset values for sysref_ctl in Table: ED Control Block Control and Status Registers.
2021.10.11 21.3 1.0.0 Initial release.
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