Achieving Timing Closure on a Design Example
Intel® Quartus® Prime may not achieve full timing closure when it first compiles and fits this designs.
Intel® Quartus® Prime assume worst-case timing parameters over a wide range of temperature, which is good practice for a commercial design. If you run this design at room temperature, it is unlikely that real timing violations occur. To achieve full timing closure with Intel® Quartus® Prime, you may include additional pipeline registers. However, the place-and-route process is sensitive to an initial seed value and the result of different seeds is not easy to predict. Before optimizing the design, try the seed sweep function with many different seed values in case the design immediately fits.