DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683887
Date 9/14/2022
Public
Document Table of Contents

1.1. Directory Structure

The directories contain the generated files for the DisplayPort design example.
Figure 2. Directory Structure for the Design Example
Table 1.  Other Generated Files in RTL Folder
Folders Files
clkrec /altera_pll_reconfig_core.v
/altera_pll_reconfig_mif_reader.v
/altera_pll_reconfig_top.v
/bitec_clkrec.qip
/bitec_clkrec.sdc
/bitec_clkrec.v
/bitec_dp_add.v
/bitec_dp_cdc.v
/bitec_dp_cdc_fifo.v
/bitec_dp_cdc_pulse.v
/bitec_dp_cnt.v
/bitec_dp_dcfifo.v
/bitec_dp_dd.v
/bitec_dp_div.v
/bitec_dp_mult.v
/bitec_fpll_calc.v
/bitec_fpll_cntrl.v
/bitec_fpll_reconf.v
/bitec_loop_cntrl.v
/bitec_vsyngen.v
/clkrec_pll135_s10.ip
/clkrec_pll_s10.ip
/clkrec_reset_s10.ip
<Platform Designer generated folder>
core /dp_core.qsys
/dp_rx.qsys
/dp_tx.qsys
<Platform Designer generated folder>
rx_phy /gxb_rx.ip
/gxb_rx_reset.ip
/rx_phy_top.v
<Platform Designer generated folder>
tx_phy /gxb_tx.ip
/gxb_tx_reset.ip
/gxb_tx_fpll.ip
/tx_phy_top.v
<Platform Designer generated folder>
Table 2.   Other Generated Files in Simulation Folder
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
cadence /cds.lib
/hdl.var
<cds_libs folder>
core /dp_core.ip
/dp_rx.ip
/dp_tx.ip
<Platform Designer generated folder>
mentor /mentor.do
/msim_setup.tcl
rx_phy /gxb_rx.ip
/rx_phy_top.v
/gxb_rx_reset.ip
<Platform Designer generated folder>
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
testbench /a10_dp_harness.sv
/clk_gen.v
/freq_check.v
/rx_freq_check.v
/tx_freq_check.v
/vga_driver.v
tx_phy /gxb_tx.ip
<Platform Designer generated folder>
/gxb_tx_fpll.ip
/gxb_tx_reset.ip
/tx_phy_top.v
xcelium /cds.lib
/hdl.var
/xcelium_sim.sh
/xcelium_setup.sh
<cds_libs folder>