F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 9/29/2025
Public
Document Table of Contents

A.6.4.2. F-Tile FGT PAM4 Tuning Flow

There are TXEQ tuning guidelines based on three insertion loss ranges below. You should know each of your channels insertion loss. If they all fall into the same insertion loss range, and the variation is less than 5dB, you can likely use the same optimal TXEQ setting for all. More than 5dB of insertion loss variation requires another tuning.

  1. Insertion Loss: 0 to 10 dB

    F-Tile FGT TX to F-Tile FGT RX Tuning Guidelines

    Start with the following steps to tune:
    1. Set the F-Tile FGT TXEQ per the table below.
    2. Measure BER for 5 samples and 5 repeats for each lane over your application’s min and max temperatures.
    3. If BER is 2 decades (*) better than the BER spec at the worst temperature found in step b, and CTLE (0-63), VGA (0-63) are not at min (0) or max value (63), tuning is complete.
      Note: (*) If the Spec BER is 10-6, 1 decade margin is 10-7.

      If BER is not meeting 2 decades better than spec margin, or CTLE, VGA are at either min (0) or max value (63), continue tuning.

        main_tap pre_tap_1 pre_tap_2 post_tap_1 QSF Assignment or Quartus® Prime Setting
      Insertion Loss <= 10dB 55 0 0 0
      set_instance_assignment -name 
      HSSI_PARAMETER "vsr_mode=
      VSR_MODE_LOW_LOSS" -to 
      <RX_SERIAL_PIN> -entity 
      <TOP_LEVEL_NAME>
      OR

      select VSR_MODE_LOW_LOSS

      in the Analog Parameters tab in the Quartus® Prime IP Parameter Editor.
    If BER is not meeting 2 decades better than spec margin, or CTLE, VGA is at either min (0) or max value (63), follow the steps below.
    1. Set the TX equalization parameters as follows:
      • pre_tap_1: 0
      • pre_tap_2: 0
      • post_tap_1: 0
    2. Sweep main_tap from full swing (55) and step down to 33 (60% of full swing) and measure the BER from 5 samples and 5 repetitions over your application’s min and max temperatures. Pick a main_tap value that gives the best average BER. Perform an RX reset for each main_tap value.
    3. Set main_tap to the value found in step b.
    4. Sweep pre_tap_1 and measure BER from 5 samples and 5 repetitions at the worst temperature found in step b. Perform an RX reset for each pre_tap_1 value.
    5. Set pre_tap_1 to the value in step d that gives the best average BER.

    Non-F-Tile FGT TX to F-Tile FGT RX Tuning Guidelines

    Start with the following steps to tune:
    1. Set the link partner (LP) TXEQ per the table below.
    2. Measure the BER for 5 samples and 5 repeats for each lane over your application's min and max temperatures.
    3. If BER is 2 decades (*) better than the BER spec at the worst temperature found in step b, and CTLE (0-63), VGA (0-63) are not at min (0) or max value (63), tuning is complete.
      Note: (*) If the Spec BER is 10-6, 1 decade margin is 10-7.

      If BER is not meeting 2 decades better than spec margin, or CTLE, VGA are at either min (0) or max value (63), continue tuning.

        C(0) C(-1) C(-2) C(1) QSF Assignment or Quartus® Prime Setting
      Insertion Loss <= 10dB 1 0 0 0
      set_instance_assignment -name 
      HSSI_PARAMETER "vsr_mode=
      VSR_MODE_LOW_LOSS" -to 
      <RX_SERIAL_PIN> -entity 
      <TOP_LEVEL_NAME>
      OR

      select VSR_MODE_LOW_LOSS in the Analog Parameters tab in the Quartus® Prime IP Parameter Editor.

    If BER is not meeting 2 decades better than spec margin, or CTLE, VGA is at either min (0) or max value (63), follow the steps below.
    1. Set the link partner’s TX equalization parameters as follows:
      • C(-1): 0
      • C(-2): 0
      • C(1): 0
    2. Sweep C(0) from full swing and step down to 60% of full swing and measure BER from 5 samples and 5 repetitions over your application’s min and max temperatures. Pick a C(0) value that gives the best average BER. Perform an RX reset for each C(0) value.
    3. Set C(0) to the value found in step b.
    4. Sweep C(-1) and measure BER from 5 samples and 5 repetitions at the worst temperature found in step b. Perform an RX reset for each C(-1) value.
    5. Set C(-1) to the value in step d that gives the best average BER.
  2. Insertion Loss: 10 to 20 dB

    F-Tile FGT TX to F-Tile FGT RX Tuning Guidelines

    Start with the following steps to tune:
    1. Set the F-Tile FGT TXEQ per the table below.
    2. Measure BER for 5 samples and 5 repeats for each lane over your application’s min and max temperatures.
    3. If BER is 2 decades better than the BER spec at the worst temperature found in step b, and CTLE (0-63), VGA (0-63) are not at min (0) or max value (63), tuning is complete.

      If BER is not meeting 2 decades better than spec margin, or CTLE, VGA are at either min (0) or max value (63), continue tuning.

        main_tap pre_tap_1 pre_tap_2 post_tap_1 QSF Assignment or Quartus® Prime Setting
      10dB < Insertion Loss <= 20dB 55 5 0 0
      set_instance_assignment -name
      HSSI_PARAMETER
      "vsr_mode=VSR_MODE_DISABLE" -to 
      <RX_SERIAL_PIN> -entity
      <TOP_LEVEL_NAME>
      OR

      select VSR_MODE_DISABLE

      in the Analog Parameters tab in the Quartus® Prime IP Parameter Editor.
    If BER is not meeting 2 decades better than spec margin, or CTLE, VGA are at either min (0) or max value (63), follow the steps below.
    1. Set pre_tap_1 to 5 (10% of full swing).
    2. Sweep main_tap from full swing (55) and step down to 33 (60% of full swing) and measure BER from 5 samples and 5 repetitions over your application's min and max temperatures. Pick a main_tap value that gives the best average BER. Perform an RX reset for each main_tap value.
    3. Set main_tap to the value found in step b.
    4. Sweep pre_tap_1 and measure BER from 5 samples and 5 repetitions at the worst temperature found in step b. Perform an RX reset for each pre_tap_1 value.
    5. Set pre_tap_1 to the value in step d that gives the best average BER.

    Non-F-Tile FGT TX to F-Tile FGT RX Tuning Guidelines

    Start with the following steps to tune:
    1. Set the link partner (LP) TXEQ per the table below.
    2. Measure BER for 5 samples and 5 repeats for each lane over your application’s min and max temperatures.
    3. If BER is 2 decades better than the BER spec at the worst temperature found in step b, and CTLE (0-63), VGA (0-63) are not at the min (0) or max value (63), tuning is complete.

      If BER is not meeting 2 decades better than the spec margin, or CTLE, VGA are at either min (0) or max value (63), continue tuning.

        C(0) C(-1) C(-2) C(1) QSF Assignment or Quartus® Prime Setting
      10dB < Insertion Loss <= 20dB 0.9 0.1 0 0
      set_instance_assignment -name
      HSSI_PARAMETER
      "vsr_mode=VSR_MODE_DISABLE" -to 
      <RX_SERIAL_PIN> -entity
      <TOP_LEVEL_NAME>
      OR

      select VSR_MODE_DISABLE

      in the Analog Parameters tab in the Quartus® Prime IP Parameter Editor.
    If BER is not meeting 2 decades better than the spec margin, or CTLE, VGA are at either min (0) or max value (63), follow the steps below.
    1. Set the link partner's TX equalization parameters as follows:
      • C(-1): 0.1
      • C(-2): 0
      • C(1): 0
    2. Sweep C(0) from full swing and step down to 60% of full swing and measure BER from 5 samples and 5 repetitions over your application’s min and max temperatures. Pick a C(0) value that gives the best average BER. Perform an RX reset for each C(0) value.
    3. Set C(0) to the value found in step b.
    4. Sweep C(-1) and measure BER from 5 samples and 5 repetitions at the worst temperature found in step b. Perform an RX reset for each C(-1) value.
    5. Set C(-1) to the value in step d that gives the best average BER.
  3. Insertion Loss: 20 to 30 dB

    F-Tile FGT TX to F-Tile FGT RX Tuning Guidelines

    Start with the following steps to tune:
    1. Set the F-Tile FGT TXEQ per the table below.
    2. Measure BER for 5 samples and 5 repeats for each lane over your application’s min and max temperatures.
    3. If BER is 2 decades better than the BER spec at the worst temperature found in step b, and CTLE (0-63), VGA (0-63) are not at min (0) or max value (63), tuning is complete.

      If BER is not meeting 2 decades better than the spec margin, or CTLE, VGA are at either min (0) or max value (63), continue tuning.

        main_tap pre_tap_1 pre_tap_2 post_tap_1 QSF Assignment or Quartus® Prime Setting
      20dB < Insertion Loss <= 30dB 55 10 2 0
      set_instance_assignment -name
      HSSI_PARAMETER
      "vsr_mode=VSR_MODE_DISABLE" -to 
      <RX_SERIAL_PIN> -entity
      <TOP_LEVEL_NAME>
      OR

      select VSR_MODE_DISABLE

      in the Analog Parameters tab in the Quartus® Prime IP Parameter Editor.
    If BER is not meeting 2 decades better than the spec margin, or CTLE, VGA are at either min (0) or max value (63), follow the steps below.
    1. Set the F-Tile FGT TX main_tap to 55 (full swing).
    2. Set the other TX equalization parameters as follows:
      • pre_tap_1: 0
      • pre_tap_2: 0
      • post_tap_1: 0
    3. Sweep pre_tap_1 and measure BER from 5 samples and 5 repetitions over your application's min and max temperatures. Pick the pre_tap_1 value that gives the best average BER. Perform an RX reset for each pre_tap_1 value.
    4. Set pre_tap_1 to the value found in step c.
    5. Sweep pre_tap_2 and measure BER from 5 samples and 5 repetitions at the worst temperature found in step c. Perform an RX reset for each pre_tap_2 value.
    6. Set pre_tap_2 to the value in step e that gives the best average BER.
    7. If BER is not meeting spec or for <50Gbps PAM4, sweep post_tap_1 and measure BER from 5 samples and 5 repetitions at the worst temperature found from step c. Perform an RX reset for each post_tap_1 value.
    8. Set post_tap_1 to the value that gives the best average BER.

    Non-F-Tile FGT TX to F-Tile FGT RX Tuning Guidelines

    Start with the following steps to tune:
    1. Set the link partner (LP) TXEQ per the table below.
    2. Measure BER for 5 samples and 5 repeats for each lane over your application’s min and max temperatures.
    3. If BER is 2 decades better than the BER spec at the worst temperature found in step b, and CTLE (0-63), VGA (0-63) are not at the min (0) or max value (63), tuning is complete.

      If BER is not meeting 2 decades better than the spec margin, or CTLE, VGA are at either min (0) or max value (63), continue tuning.

        C(0) C(-1) C(-2) C(1) QSF Assignment or Quartus® Prime Setting
      20dB < Insertion Loss <= 30dB 0.79 0.18 0.03 0
      set_instance_assignment -name
      HSSI_PARAMETER
      "vsr_mode=VSR_MODE_DISABLE" -to 
      <RX_SERIAL_PIN> -entity
      <TOP_LEVEL_NAME>
      OR

      select VSR_MODE_DISABLE

      in the Analog Parameters tab in the Quartus® Prime IP Parameter Editor.
    If BER is not meeting 2 decades better than the spec margin, or CTLE, VGA are at either min (0) or max value (63), follow the steps below.
    1. Set the link partner's TX C0 to 1 (full swing).
    2. Set the other TX equalization parameters as follows:
      • C(-1): 0
      • C(-2): 0
      • C(1): 0
    3. Sweep C(-1) and measure BER from 5 samples and 5 repetitions over your application’s min and max temperatures. Pick the C(-1) value that gives the best average BER. Perform an RX reset for each C(-1) value.
    4. Set C(-1) to the value found in step c.
    5. Sweep C(-2) and measure BER from 5 samples and 5 repetitions at the worst temperature found in step c. Perform an RX reset for each C(-2) value.
    6. Set C(-2) to the value in step e that gives the best average BER.
    7. If BER is not meeting spec or for <50Gbps PAM4, sweep C(1) and measure BER from 5 samples and 5 repetitions at the worst temperature found in step c. Perform an RX reset for each C(1) value.
    8. Set C(1) to the value that gives the best average BER.