F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 9/29/2025
Public
Document Table of Contents

3.14.1.3. Obtaining BER Values for Production Devices

Enabling the TX PRBS Generator

To enable the TX PRBS generator for lane 0, follow these steps:

  1. Set car_tx_clk_src_sel (0x60000[5:2]) to 4’b1.
  2. Set car_dft_tx_clken (0x40000[10]) to 1'b1. If using multi-lanes, set 1'b1 to all lanes.
  3. Set car_dft_tx_swrstb (0x40004[13]) to 1'b1. If using multi-lanes, set 1'b1 to all lanes.
  4. Set cfg_lane_tx_prbs_mode (0x4292C[4:1]) to:
    • 4’d0: PRBS 7
    • 4’d1: PRBS 9
    • 4’d2: PRBS 11
    • 4’d3: PRBS 23
    • 4’d4: PRBS 31
    • 4'd5: PRBS 58
    • 4'd6: PRBS 13
    • 4'd7: PRBS 15

    If using multi-lanes, set the desired values to all lanes.

  5. Set cfg_tx_bus_take_dft (0x45804[0]) to 1'b1. If using multi-lanes, set 1'b1 to all lanes.
  6. Set cfg_lane_tx_prbs_en (0x4292C[0]) to 1'b1. If using multi-lanes, set 1'b1 to all lanes.
  7. Set cfg_lane_tx_prbs_init (0x42934[0]) to 1'b1. If using multi-lanes, set 1'b1 to all lanes.
  8. Set cfg_prbs_mask_msb (0x4293C[31:0]) to 32'b0. If using multi-lanes, set 32'b0 to all lanes.
  9. Set cfg_prbs_mask_lsb (0x42938[31:0]) to 32'b0. If using multi-lanes, set 32'b0 to all lanes.

Enabling RX PRBS Verifier

To enable the RX PRBS verifier for lane 0, follow these steps:
  1. Read cfg_dp_rx_width (0x45860 [7:5]) to obtain the width of the read data width of the design.
    • If width = 0; mode = 0
    • If width = 1; mode = 2
    • Else mode = 3
    Mode can also be interpreted as:
    • Mode 0: 100G_PAM4
    • Mode 1: 56G_PAM4
    • Mode 2: 56G_PAM2
    • Mode 3: 25G_PAM2
  2. Set car_dft_rx_clken (0x40000[4]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  3. Set car_dft_rx_swrstb (0x40004 [8]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  4. Set cfg_dft_rx_prbs_common_en (0x42928 [0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  5. Set cfg_dft_rx_prbs_sel (0x42928 [4:1]) to:
    • 4’d0: PRBS 7
    • 4’d1: PRBS 9
    • 4’d1: PRBS 9
    • 4’d4: PRBS 31
    • 4'd5: PRBS 58
    • 4'd6: PRBS 13
    • 4'd7: PRBS 15
    If using multi-lanes, specify value for all lanes.

Initializing the BER Counters

To initialize the BER counters for BER computation for lane 0, follow these steps:
  1. Set cfg_dft_rx_unlock_dly_sel (0x428D4 [12:10]) to 3’b111. If using multi-lanes, set 3’b111 to all lanes.
  2. Set cfg_dft_rx_data_sel (0x42928 [6:5]) to
    • 2’b00: 100G_PAM4
    • 2’b01: 56G_PAM4
    • 2’b10: 56G_PAM2
    • 2’b11: 25G_PAM2
    If using multi-lanes, set the required values as mentioned above to all lanes.
  3. Set the number of symbols = 0 or 1e^9 depending on if you want the BER for the free-running mode or symbol limit mode.
  4. Set cfg_ber_symb_cnt_limit_lsb (0x428E4[31:0]) to 32'b0 for free running mode. If using multi-lanes, set 32'b0 to all lanes.
  5. Set cfg_ber_symb_cnt_limit_msb (0x428E8[31:0]) to 32'b0 for free running mode. If using multi-lanes, set 32'b0 to all lanes.
  6. Set cfg_dft_ber_count_mode (0x428D4 [2:1]) to 2’b11 for free-running mode. If using multi-lanes, set 2’b11 to all lanes.
  7. Set cfg_ber_cnt_limit_lsb (0x428E4[31:0]) to (int(int(1e^9/) & 0xFFFFFFFF)); for symbol limit mode. If using multi-lanes, set the above value to all lanes.
  8. Set cfg_ber_cnt_limit_msb (0x428E8[31:0]) to (int(int(1e^9/(2^32)) & 0xFFFFFFFF)); for symbol limit mode. If using multi-lanes, set the above value to all lanes.
  9. Set cfg_dft_ber_count_mode (0x428D4[2:1]) to 2'b1. If using multi-lanes, set the above value to all lanes.
  10. Set cfg_dft_ber_count_en (0x428D4 [0]) to 1’b1. If using multi-lanes, set 1’b1 to all lanes.
  11. Read cfg_dp_rx_width (0x45860 [7:5]) to obtain the width of the read data in your design.
    • If width = 0; mode = 0
    • If width = 1; mode = 2
    • Else mode = 3
    Mode can also be interpreted as:
    • Mode 0: 100G_PAM4
    • Mode 1: 56G_PAM4
    • Mode 2: 56G_PAM2
    • Mode 3: 25G_PAM2
  12. Based on mode obtained in step 10:

    If mode = 1 or mode = 2:

    • Set cfg_dft_ber_error_mask_0_31 (0x428DC [31:0]) to 0xFFFFFFFF. If using multi-lanes set all lanes to 0xFFFFFFFF.
    • Set cfg_dft_ber_error_mask_32_63 (0x428E0 [31:0] to 0xFFFFFFFF. If using multi-lanes set all lanes to 0xFFFFFFFF.
    If mode = 3:
    • Set cfg_dft_ber_error_mask_0_31 (0x428DC [31:0]) to 0xFFFFFFFF. If using multi-lanes, set all lanes to 0xFFFFFFFF
    • Set cfg_dft_ber_error_mask_32_63 (0x428E0 [31:0]) to 0xFFFFFFFF. If using multi-lanes, set all lanes to 0xFFFFFFFF
    • Set cfg_dft_ber_error_mask_64_95 (0x42960 [31:0]) to 0xFFFFFFFF. If using multi-lanes, set all lanes to 0xFFFFFFFF.
    Else:
    • Set cfg_dft_ber_error_mask_0_31 (0x428DC [31:0]) to 32’b0. If using multi-lanes, set all lanes to 32’b0.
    • Set cfg_dft_ber_error_mask_32_63 (0x428E0 [31:0]) to 32’b0. If using multi-lanes, set all lanes to 32’b0.
    • Set cfg_dft_ber_error_mask_64_95 (0x42960 [31:0]) to 32’b0. If using multi-lanes, set all lanes to 32’b0.
    • Set cfg_dft_ber_error_mask_96_127 (0x42964 [31:0]) to 32’b0. If using multi-lanes, set all lanes to 32’b0.
  13. Give a delay of 1000ms after setting the error masks before starting, clearing, or stopping the BER counters.
  14. Set cfg_dft_ber_stop_c (0x428D8 [2]) to 1’b1. If using multi-lanes, set all lanes to 1’b1.
  15. Set cfg_dft_ber_clear_c (0x428D8 [0]) to 1’b1. If using multi-lanes, set all lanes to 1’b1.
  16. Set cfg_dft_ber_start_c (0x428D8 [1]) to 1’b1. If using multi-lanes, set all lanes to 1’b1.

Calculating the BER Values

To calculate the errors for BER computation for lane 0, follow these steps:
  1. Read dft_ber_csv_rcv_error_global_lsb (0x428F0 [31:0]) to obtain the LSB of global errors. If using multi-lanes, read all lanes.
  2. Read dft_ber_csv_rcv_error_global_msb (0x428F4 [15:0]) to obtain the MSB of global errors. If using multi-lanes, read all lanes.
  3. Read cfg_ber_symb_cnt_limit_lsb (0x428E4 [31:0]) to obtain the LSB of symbol limit. If using multi-lanes, read all lanes.
  4. Read cfg_ber_symb_cnt_limit_msb (0x428E8 [31:0]) to obtain the MSB of symbol limit. If using multi-lanes, read all lanes.
  5. To compute errors:
    • Error = (read data from step 2 x (2 ^ 32)) + (read data from step 1)
  6. To compute symbol limit:
    • Sym_limit = (read data from step 4 x (2 ^ 32)) + (read data from step 3)
  7. Computing bits per symbol using the mode obtained from step 5. of initialization of the BER counters:
    • If mode = 1 or mode = 2; bit_per_symbol = 64
    • If mode = 3; bit_per_symbol = 32
    • Else bit_per_symbol = 128
  8. To calculate BER:
    • BER = Error (from step 5.) / ((Sym_limit (from step 6.)) x bit_per_symbol (from step 7.))