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Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides
1.1. FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Flows
1.5. Supported Hardware Description Languages
1.6. Supported Simulation Types
1.7. Supported Simulators
1.8. Post-Fit Simulation Support by FPGA Family
1.9. Automating Simulation with the Run Simulation Feature
1.10. FPGA Simulation Basics Revision History
1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
1.9.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
1.9.2.3. Launching Simulation with the Run Simulation Feature
1.9.2.4. Running RTL Simulation using Run Simulation
1.9.2.5. Output Directories and Files for Run Simulation
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1.6. Supported Simulation Types
You can run different types of simulation, depending on the stage of the Quartus® Prime design flow:
Simulation Type | Description | Occurs |
---|---|---|
RTL | Simulation of an RTL design consisting of one or more RTL files that you provide as input to the Quartus® Prime software. These RTL files typically also include the files that the Quartus® Prime Platform Designer generates for Intel® FPGA IP and systems. You can only simulate HDL RTL files.2. The RTL files can instantiate low level blocks, such as primitives, basic IP functions, and ATOMs, as Quartus Prime Simulation Library describes. | Can perform before Quartus® Prime Synthesis |
Post-Synthesis Simulation (Gate-Level) | The Quartus® Prime software can generate a Verilog HDL or VHDL gate-level netlist after the synthesis stage completes, but before the Fitter stage runs. The resulting netlist is the post-synthesis netlist. The Quartus® Prime EDA Netlist Writer tool generates the post-synthesis netlist. The post-synthesis netlist is a netlist of low level blocks called ATOMs. The post-synthesis netlist is a purely functional netlist. | Must perform after Quartus® Prime synthesis |
Post-Fit Simulation (Gate-Level) | The Quartus® Prime EDA Netlist Writer can generate a Verilog HDL or VHDL gate-level netlist after the Fitter stage completes. The resulting netlist is the post-fit netlist. The post-fit netlist is a netlist of ATOMs that the Fitter placed and routed on the FPGA device. The post-fit netlist is a purely functional netlist.
Note: The post-fit netlist includes chip locations of ATOM instances in commented lines. The post-synthesis netlist does not include this data.
|
Must perform after Quartus® Prime Fitter |
Note: the Quartus® Prime software supports post-fit functional simulation, but does not support post-fit timing simulation.
2 You must first convert the non-HDL files to HDL files prior to simulation