eCPRI Intel® FPGA IP Design Example User Guide

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ID 683837
Date 12/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. eCPRI Intel® FPGA IP Design Example User Guide Archives 4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the eCPRI Intel FPGA IP Design Example 1.8. Generating and Downloading the Executable and Linking Format (.elf) Programming File
1.4. Simulating the Design Example Testbench x
1.4.1. Enabling Dynamic Reconfiguration to the Ethernet IP
2. Design Example Description x
2.1. Features 2.2. eCPRI IP Hardware Design Example 2.3. Simulation Design Example 2.4. eCPRI IP Design Example Interface Signals 2.5. Design Example Register Map
1. Quick Start Guide
2. Design Example Description
3. eCPRI Intel® FPGA IP Design Example User Guide Archives
4. Document Revision History for the eCPRI Intel® FPGA IP Design Example User Guide

1.5. Compiling the Compilation-Only Project

To compile the compilation-only example project, follow these steps:

  1. Ensure compilation design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime Pro Edition project <design_example_dir>/synthesis/quartus/ecpri_ed.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, reports for timing and for resource utilization are available in your Quartus® Prime Pro Edition session. Go to Processing > Compilation Report to view the detailed report on compilation.
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