F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 9/26/2022
Public

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4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training

This design example describes necessary steps to enable auto-negotiation and link training (AN/LT) in your design example.

When you enable auto-negotiation and link training parameter in the IP and generate a design example, the design example instantiates two separate IPs, F-Tile Ethernet Intel FPGA Hard IP and the F-Tile Auto-Negotiation and Link Training for Ethernet. You must connect required signals at the top level of your testbench.

The following IP parameter settings were used to generate this design example:
Table 10.   F-Tile Ethernet Intel FPGA Hard IP Parameter SettingsTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
General Options
PMA type FGT
Ethernet mode 100GE-4
Client interface MAC segmented
FEC mode IEEE 802.3 RS(528,514) (CL91)
PMA reference frequency 156.25 MHz
System PLL frequency 805.6640625 MHz
Table 11.   F-Tile Auto-Negotiation and Link Training for Ethernet Parameter SettingsTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
Mode Selection
Enable auto-negotiation on reset

On

Enable link training on reset

On

PMA type FGT
Ethernet mode 100GE-4
KR or CR mode KR mode
Number of ports 1
FEC mode IEEE 802.3 RS(528,514)
Status clock frequency 100 MHz

For more information about steps of how to generate a design example, refer to the Generating the Design Example.

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