Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

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ID 683791
Date 4/07/2025
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1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.2.1] [P-Tile: v8.3.1] [F-Tile: v9.3.1] [R-Tile: v5.3.1]] 1.2. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.2.0] [P-Tile: v8.3.0] [F-Tile: v9.3.0] [R-Tile: v5.3.0] 1.3. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.2.0] [P-Tile: v8.2.0] [F-Tile: v9.2.0] [R-Tile: v5.2.0] 1.4. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.1.0] [P-Tile: v8.1.0] [F-Tile: v9.1.0] [R-Tile: v5.1.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v23.1.0] [P-Tile: v7.1.0] [F-Tile: v8.0.0] [R-Tile: v4.1.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v23.0.0] [P-Tile: v7.0.0] [F-Tile: v7.0.0] [R-Tile: v4.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.3.0] [P-Tile: v6.0.0] [F-Tile: v6.0.0] [R-Tile: v3.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.2.0] [P-Tile: v5.1.0] [F-Tile: v5.1.0] [R-Tile: v2.0.0] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.1.0] [P-Tile: v5.0.0] [F-Tile: v5.0.0] [R-Tile: v1.0.0] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v22.0.0] [P-Tile: v4.0.0] [F-Tile: v4.0.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.5.0 ] [P-Tile: v3.1.0 ] [F-Tile: v3.0.0 ] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.4.0 ] [P-Tile: v3.0.0] [F-Tile: v2.0.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.3.0] [P-Tile: v2.2.0] [F-Tile: v1.1.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: v21.2.0] [P-Tile: v2.1.0] [F-Tile: v1.0.0] 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.16. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.17. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.18. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.2. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: v24.2.0] [P-Tile: v8.3.0] [F-Tile: v9.3.0] [R-Tile: v5.3.0]

Table 2.  [H-Tile: v24.2.0] [P-Tile: v8.3.0] [F-Tile: v9.3.0] [R-Tile: v5.3.0] : 2025.01.27
Quartus® Prime Version Description Impact
24.3.1 Added support for the R-Tile MCDMA 2x8 Root Port mode for p0_int and p1_int. Enabling both instances exposes the interrupt signals p0_irq_status_o and p1_irq_status_o.
Updated the instructions to compile the DPDK driver for the R-Tile MCDMA 2x8. For more details, refer to the Multichannel DMA Intel® FPGA IP for PCI Express* Design Example User Guide.
Added design example simulation support for the R-Tile PIO with MCDMA Bypass Mode with Questasim*. When this support is enabled, the R-Tile MCDMA IP exposes the PIPE interface. Added the Questasim command in the User Guide. For additional details, refer to the Multichannel DMA Intel® FPGA IP for PCI Express* Design Example User Guide.
The F-Tile MCDMA Hard IP Reconfiguration interface is supported for p0 and p1. Both can be enabled in the Quartus® Prime IP Parameter Editor. For more details, refer to the Multichannel DMA Intel® FPGA IP for PCI Express* Design Example User Guide.
The R-Tile MCDMA supports Configuration via Protocol (CvP) in both the Avalon® Streaming IP for PCI Express* and Multichannel DMA IP for PCI Express*. You can enable CvP for both types of IP. For more details, refer to the Multichannel DMA Intel® FPGA IP for PCI Express* Design Example User Guide.
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