Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide

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ID 683747
Date 7/12/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives 3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design Example 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
1.1. Generating the Design Example x
1.1.1. Design Example Parameters
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Low Latency E-Tile 40G Ethernet Design Example Registers 2.7. Design Example Interface Signals
2.5. Hardware Testing x
2.5.1. Internal Loopback Test 2.5.2. External Loopback Test
1. Quick Start Guide
2. Design Example Description
A. Low Latency E-Tile 40G Ethernet Intel FPGA IP Archives
3. Document Revision History for Low Latency E-Tile 40G Ethernet Design Example User Guide

1.2. Directory Structure

The Low Latency E-Tile 40G Ethernet IP core design example file directories contain the following generated files for the design example.

Figure 4. Directory Structure for the Generated Design Example
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
  • The compilation-only example design is located in <design_example_dir>/compilation_test_design.
  • The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
Table 2.  Directory and File Descriptions

File Names

Description

eth_ex_40g.qpf Quartus® Prime project file.
eth_ex_40g.qsf Quartus® Prime project settings file.
eth_ex_40g.sdc Synopsys* Design Constraints file. You can copy and modify this file for your own Low Latency E-Tile 40G Ethernet Intel® FPGA IP design.
eth_ex_40g.srf Quartus® Prime project message suppression rule file.
eth_ex_40g.v Top-level Verilog HDL design example file.
eth_ex_40g_clock.sdc Synopsys* Design Constraints file for clocks.
common/ Hardware design example support files.
hwtest/main.tcl

Main file for accessing System Console.
Level Two Title