Quartus® Prime Pro Edition: Version 25.3 Software and Device Support Release Notes

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ID 683706
Date 10/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quartus® Prime Pro Edition Version 25.3 Software and Device Support Release Notes
1. Quartus® Prime Pro Edition Version 25.3 Software and Device Support Release Notes x
1.1. New Features and Enhancements 1.2. Changes to Software Behavior 1.3. Altera IP Regeneration 1.4. Operating System Support 1.5. Disk Space and Memory Recommendations 1.6. Quartus® Prime Licensing Information 1.7. Device Support and Pin-Out Status 1.8. Timing Model, Power Model, and Device Model Status 1.9. Altera® FPGA SDM Firmware 1.10. IBIS Models 1.11. EDA Interface Information 1.12. Antivirus Verification 1.13. Software Issues Resolved 1.14. Software Patches Included in this Release 1.15. Latest Known Quartus® Prime Software Issues 1.16. Latest Known Altera® FPGA SDM Firmware Issues 1.17. Quartus® Prime Pro Edition Software and Device Support Release Notes Archives 1.18. Quartus® Prime Pro Edition Software Release Version 25.3 Document Revision History
1.2. Changes to Software Behavior x
1.2.1. Deprecated Features and Functions 1.2.2. Removed Features and Functions
1.7. Device Support and Pin-Out Status x
1.7.1. Devices with Final Device Support 1.7.2. Devices with Preliminary Device Support 1.7.3. Devices with Advance Device Support 1.7.4. Changes in Device Support
1. Quartus® Prime Pro Edition Version 25.3 Software and Device Support Release Notes

1.15. Latest Known Quartus® Prime Software Issues

Information about known issues that affect Quartus® Prime Pro Edition Version 25.3 is available in the Intel FPGA Knowledge Base.

For the latest information about issues that affect Quartus® Prime Pro Edition Version 25.3, review the FPGA Knowledge Base articles that apply to Quartus® Prime Pro Edition Version 25.3 .

Table 43.  Important Known Issues Affecting Quartus® Prime Pro Edition Version 25.3
Description Workaround

KEEP attributes on SystermVerilog interfaces are now honored and a wire LUT might be inserted on each ports in the interface to keep the name. This wire LUT insertion might cause fMAX issues, especially if the interface contains a clock because a wire LUT is inserted in the clock network.

 Remove the KEEP attribute from interface ports.

You can find known issue information for previous versions of the Quartus® Prime software on the FPGA Knowledge Base web page.

Information about known software issues that affect previous versions of the Quartus® II software is available on the Quartus® Prime and Quartus II Software Support web page.

Information about issues affecting the Intel® FPGA IP Library is available in the release notes for each IP. You can find the IP release notes on the FPGA Documentation Index web page.

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