eCPRI Intel® FPGA IP User Guide

Download PDF
ID 683685
Date 12/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the eCPRI IP 2. Getting Started 3. eCPRI IP Parameters 4. Functional Description 5. Interfaces 6. eCPRI IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for the eCPRI Intel® FPGA IP User Guide
1. About the eCPRI IP x
1.1. eCPRI Intel® FPGA IP Features 1.2. eCPRI IP Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. eCPRI IP Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. eCPRI IP Release Information
2. Getting Started x
2.1. Installing and Licensing the eCPRI IP 2.2. Specifying the eCPRI IP Parameters 2.3. eCPRI IP Generated File Structure 2.4. Simulating the eCPRI IP 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the eCPRI IP Parameters x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. High Level Data Path Flow 4.2. Operation of the eCPRI IP Blocks
4.1. High Level Data Path Flow x
4.1.1. Transmit TX Path 4.1.2. Receive RX Path 4.1.3. Supported Ethernet Variants
4.2. Operation of the eCPRI IP Blocks x
4.2.1. Packet Classifier 4.2.2. Ethernet Header Insertion/Removal 4.2.3. Concatenation/De-concatenation 4.2.4. Header Mapper/De-Mapper 4.2.5. eCPRI IWF Type 0 4.2.6. eCPRI Message 5 Packet Parser 4.2.7. Packet Queue 4.2.8. eCPRI Message Type 4.2.9. Error Handling 4.2.10. RX Throttling
4.2.8. eCPRI Message Type x
4.2.8.1. eCPRI Message Type 0- IQ Data Transfer 4.2.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.2.8.3. eCPRI Message Type 2- Real Time Control Data 4.2.8.4. eCPRI Message Type 3- Generic Data Transfer 4.2.8.5. eCPRI Message Type 4- Remote Memory Access 4.2.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.2.8.7. eCPRI Message Type 6- Remote Reset 4.2.8.8. eCPRI Message Type 7- Event Indication 4.2.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interfaces x
5.1. eCPRI IP Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals 5.7.4. F-Tile Ethernet Hard IP 1588 PTP Signals 5.7.5. Agilex 5 Device Ethernet Hard IP 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. About the eCPRI IP
2. Getting Started
3. eCPRI IP Parameters
4. Functional Description
5. Interfaces
6. eCPRI IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for the eCPRI Intel® FPGA IP User Guide

1.4. eCPRI IP Resource Utilization

Intel generates the resources for the IP with the Quartus® Prime Pro Edition software version 24.1 with advance mapping enabled.
Table 5.  Resource Utilization
Device L2/L3 Parser Streaming Pair with O-RAN Packets Arbitration Scheme Interworking Function (IWF) Support ALMs Dedicated Logic Registers Memory 20K
Agilex™ 5 On Off Off Fixed Off 9,305 22,546 51
On On Off Fixed Off 9,088 23,890 50
Off On Off - Off 7,987 17,912 31
Off Off Off - Off 8,165 18,203 32
On Off On Fixed Off 7,224 17,905 41
On Off On L2COS Off 12,353 25,731 41
On On Off Fixed On 10,838 24,814 70
Agilex™ 7 On Off Off Fixed Off 9,509 22,258 51
On On Off Fixed Off 9,310 22,320 50
Off On Off - Off 7,994 17,933 31
Off Off Off - Off 8,156 18,173 32
On Off On Fixed Off 7,468 17,125 41
On Off On L2COS Off 12,682 27,207 41
On On Off Fixed On 11,087 24,142 70
Agilex™ 9 On Off Off Fixed Off 9,299 22,020 51
On On Off Fixed Off 9,061 22,835 50
Off On Off - Off 7,981 18,004 31
Off Off Off - Off 8,203 18,315 32
On Off On Fixed Off 7,248 16,946 41
On Off On L2COS Off 12,400 27,290 41
On On Off Fixed On 10,837 23,914 70
Stratix® 10 On Off Off Fixed Off 9,542 22,451 51
On On Off Fixed Off 9,365 22,060 50
Off On Off - Off 7,989 17,783 31
Off Off Off - Off 8,160 18,037 32
On Off On Fixed Off 7,560 17,331 41
On Off On L2COS Off 12,947 29,062 41
On On Off Fixed On 11,159 24,350 71
Arria® 10 On Off Off Fixed Off 8,685 20,653 51
On On Off Fixed Off 8,769 20,018 50
Off On Off - Off 7,571 16,949 31
Off Off Off - Off 7,753 17,540 32
On Off On Fixed Off 6,868 15,561 41
On Off On L2COS Off 11,505 19,011 41
On On Off Fixed On 10,134 21,842 66
Level Two Title