eCPRI Intel® FPGA IP User Guide

ID 683685
Date 5/19/2023

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Document Table of Contents

1.1. Supported Features

The eCPRI Intel® FPGA IP core offers the following features:
  • Compliant with the eCPRI Specification V2.0 (2018-06-25) available on the CPRI Industry Initiative (CII) website.
  • Supports eCPRI radio equipment controller (eREC) and eCPRI radio equipment (eRE) module configurations.
  • Supports Ethernet headers in a variety of formats, including VLAN tag, source/destination MAC address, IPv4, UDP extraction and encapsulation.
  • Supports eCPRI one-way delay measurement based on IEEE Standard 1588 Precision Time Protocol (1588 PTP) hardware timestamp. Full hardware support, and required 1588 PTP software stack.
  • Supports 25 Gbps and 10 Gbps Ethernet ports.
  • Supports pairing of eCPRI Intel FPGA IP with O-RAN Intel FPGA IP.
  • Supports interworking function (IWF) type 0 between eCPRI node and one CPRI node.
  • Capable of streaming Ethernet frame size up to 9,000 bytes as defined by Ethernet jumbo frames standard.
  • Packet classifier responsible to classify eCPRI packet and send packets to eCPRI IP. All other packets are redirected to external port for user processing.
  • Programmable packet queue (maximum 16 entries) to hold incoming packets when eCPRI packets transmission in progress.
  • Arbitration between eCPRI packet and external incoming Ethernet frames, e.g., Control & Management (C&M) and synchronization packets.
  • Offers mapping logic between eCPRI message physical channel ID to VLAN/MAC address CSR.
  • Supports single distributed unit (DU) and up to eight radio unit (RU) configurations using source/destination MAC address CSR.
  • Support all eCPRI message types compliant to eCPRI specification v2.0
  • Input/output ports compliant with Avalon® streaming interface .
Table 1.   eCPRI Intel® FPGA IP Feature Matrix
Device Support Data Rate
Intel® Agilex™ 7 25G
Intel® Stratix® 10 25G
Intel® Arria® 10 10G