| 2023.06.26 |
23.2 |
21.1.1 |
Added VHDL support for synthesis and simulation model. |
| 2022.08.03 |
21.3 |
20.0.1 |
Corrected the device OPN for the Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit. |
| 2021.10.04 |
21.3 |
20.0.1 |
- Added support for QuestaSim* simulator.
- Removed support for NCSim simulator.
|
| 2021.02.24 |
20.4 |
20.0.1 |
- Added information about preserving the unused transceiver channel for PAM4 in section: Hardware Design Example Components.
- Added the pll_ref_clk[1] signal description in section: Interface Signals.
|
| 2020.12.14 |
20.4 |
20.0.0 |
- Updated sample hardware test output for Interlaken mode and Interlaken Look-aside mode in section Testing the Hardware Design Example.
- Updated register map for Interlaken Look-aside design example in section Register Map.
- Added a passing criteria for a successful hardware test run in section Testing the Hardware Design Example.
|
| 2020.10.16 |
20.2 |
19.3.0 |
Following changes made in Testing the Hardware Design Example section:
- Added a note to turn on internal serial loopback in H-tile IP variations.
- Corrected command to run the initial adaptation calibration on RX side.
|
| 2020.06.22 |
20.2 |
19.3.0 |
- The design example is available for Interlaken Look-aside mode.
- Added Figure: High-level Block Diagram for Interlaken (2nd Generation) Design Example.
- Updated following sections:
- Hardware and Software Requirements
- Directory Structure
- Modified the following figures to include Interlaken Look-aside related update:
- Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations
- Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations
- Updated Figure: IP Parameter Editor.
- Added test run outputs for the Interlaken Look-aside in the following sections:
- Simulating the Design Example Testbench
- Testing the Hardware Design Example
- Added information about the frequency settings in the clock control application in section Compiling and Configuring the Design Example in Hardware.
- Added following new signals in Interface Signals section:
- mgmt_clk
- tx_pin_n
- rx_pin_n
- mac_clk_pll_ref
- Added register map for Interlaken Look-aside design example in section: Register Map.
|
| 2020.03.10 |
19.3 |
19.2.1 |
Corrected ATX PLL connection in Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for L-tile and H-tile 25.3 and 25.8 Gbps Variations . |
| 2019.09.30 |
19.3 |
19.2.1 |
Removed clk100. The mgmt_clk serves as a reference clock to the IO PLL in the following:
- Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations.
- Figure: Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations.
|
| 2019.04.19 |
18.1.1 |
18.1.1 |
Fixed typos in the section Hardware Design Example Components. |
| 2018.12.24 |
18.1.1 |
18.1.1 |
- Added new PMA adaptation feature in Intel® Stratix® 10 E-tile device variations.
- Added a note in Testing the Hardware Design Example section about system console command that performs initial adaptation.
|
| 2018.09.24 |
18.1 |
18.1 |
- Renamed the document title to Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP Design Example User Guide.
- Added support for Intel® Stratix® 10 devices with E-tile transceivers.
- Intel® Stratix® 10 TX and GX Transceiver Signal Integrity Development Kit support is now available to test the design example on hardware.
- Modified Figure: Directory Structure of the Generated Example Design.
- Added Table: Interlaken (2nd Generation) IP Core Hardware Design Example File Descriptions and Table: Table: Interlaken (2nd Generation) IP Core Testbench File Descriptions.
- Added support for Cadence Xcelium Parallel Simulator.
- Added new section Hardware Design Example Components
- Added a note in Generating the Design section to clarify hardware support provided with the design example.
- Update the Simulating the Design Example Testbench section to include:
- Scripts to run NCSim and Xcelium simulations.
- Design example testbench function.
- Added sample output of a successful simulation test run.
- Added new section Testing the Hardware Design Example.
- Added following register information in Table: Design Example Register Map:
- ECC error count
- ECC corrected error count
- TX SOP Count
- TX EOP Count
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