Quartus® Prime Pro Edition User Guide: Design Optimization

Download PDF
ID 683641
Date 4/17/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. Design Optimization Overview 2. Optimizing the Design Netlist 3. Netlist Optimizations and Physical Synthesis 4. Area Optimization 5. Timing Closure and Optimization 6. Analyzing and Optimizing the Design Floorplan 7. Using the ECO Compilation Flow 8. Quartus® Prime Pro Edition Design Optimization User Guide Archives A. Quartus® Prime Pro Edition User Guides
1. Design Optimization Overview x
1.1. Initial FPGA Device Considerations 1.2. Initial Compiler Settings 1.3. Optimization Trade-Offs and Limitations 1.4. Design Visualization and Optimization Tools 1.5. Design Optimization Overview Revision History
1.1. Initial FPGA Device Considerations x
1.1.1. Device Migration Considerations
1.2. Initial Compiler Settings x
1.2.1. Initial I/O Assignment Guidelines 1.2.2. Initial Timing Constraint Guidelines
1.3. Optimization Trade-Offs and Limitations x
1.3.1. Area Reduction Trade-Offs 1.3.2. Critical Path Delay Reduction Trade-Offs 1.3.3. Power Consumption Reduction Trade-Offs 1.3.4. Compilation Time Trade-Offs
1.4. Design Visualization and Optimization Tools x
1.4.1. Design Visualization Tools 1.4.2. Design Optimization Tools
2. Optimizing the Design Netlist x
2.1. When to Use the Netlist Viewers: Analyzing Design Problems 2.2. Quartus® Prime Design Flow with the Netlist Viewers 2.3. RTL Viewer Overview 2.4. Technology Map Viewer Overview 2.5. Netlist Viewer User Interface 2.6. Schematic View 2.7. Cross-Probing to a Source Design File and Other Quartus® Prime Windows 2.8. Cross-Probing to the Netlist Viewers from Other Quartus® Prime Windows 2.9. Viewing a Timing Path 2.10. Optimizing the Design Netlist Revision History
2.3. RTL Viewer Overview x
2.3.1. Maximizing Readability in RTL Viewer 2.3.2. Running the RTL Viewer
2.5. Netlist Viewer User Interface x
2.5.1. Netlist Navigator Pane 2.5.2. Properties Pane 2.5.3. Netlist Viewers Find Pane
2.6. Schematic View x
2.6.1. Display Schematics in Multiple Tabbed View 2.6.2. Schematic Symbols 2.6.3. Select Items in the Schematic View 2.6.4. Shortcut Menu Commands in the Schematic View 2.6.5. Filtering in the Schematic View 2.6.6. View Contents of Nodes in the Schematic View 2.6.7. Moving Nodes in the Schematic View 2.6.8. View LUT Representations in the Technology Map Viewer 2.6.9. Zoom Controls 2.6.10. Navigating with the Bird's Eye View 2.6.11. Partition the Schematic into Pages 2.6.12. Follow Nets Across Schematic Pages
3. Netlist Optimizations and Physical Synthesis x
3.1. Physical Synthesis Optimizations 3.2. Applying Netlist Optimizations 3.3. Scripting Support 3.4. Netlist Optimizations and Physical Synthesis Revision History
3.1. Physical Synthesis Optimizations x
3.1.1. Disabling or Enabling Physical Synthesis Optimization 3.1.2. Physical Synthesis Options
3.2. Applying Netlist Optimizations x
3.2.1. WYSIWYG Primitive Resynthesis
3.3. Scripting Support x
3.3.1. Synthesis Netlist Optimizations 3.3.2. Physical Synthesis Optimizations
4. Area Optimization x
4.1. Resource Utilization Information 4.2. Optimizing Resource Utilization 4.3. Scripting Support 4.4. Area Optimization Revision History
4.1. Resource Utilization Information x
4.1.1. Flow Summary Report 4.1.2. Fitter Reports 4.1.3. Design Assistant Recommendations 4.1.4. Analysis and Synthesis Reports 4.1.5. Compilation Messages 4.1.6. Chip Planner Visualization
4.1.2. Fitter Reports x
4.1.2.1. Route Stage Reports
4.1.2.1. Route Stage Reports x
4.1.2.1.1. Nets with Highest Wire Count Report 4.1.2.1.2. Delay Chain Summary Report 4.1.2.1.3. Top Congested Hierarchies and Nets Reports 4.1.2.1.4. Global Route Reports
4.2. Optimizing Resource Utilization x
4.2.1. Resource Utilization Issues Overview 4.2.2. I/O Pin Utilization or Placement 4.2.3. Logic Utilization or Placement 4.2.4. Routing
4.2.2. I/O Pin Utilization or Placement x
4.2.2.1. Guideline: Modify Pin Assignments or Choose a Larger Package
4.2.3. Logic Utilization or Placement x
4.2.3.1. Guideline: Optimize Source Code 4.2.3.2. Guideline: Optimize Synthesis for Area, Not Speed 4.2.3.3. Guideline: Restructure Multiplexers 4.2.3.4. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 4.2.3.5. Guideline: Use Register Packing 4.2.3.6. Guideline: Remove Fitter Constraints 4.2.3.7. Guideline: Flatten the Hierarchy During Synthesis 4.2.3.8. Guideline: Re-target Memory Blocks 4.2.3.9. Guideline: Use Physical Synthesis Options to Reduce Area 4.2.3.10. Guideline: Retarget or Balance DSP Blocks 4.2.3.11. Guideline: Use a Larger Device 4.2.3.12. Guideline: Reduce Global Signal Congestion 4.2.3.13. Guideline: Report Pipelining Information
4.2.4. Routing x
4.2.4.1. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 4.2.4.2. Guideline: Set Fitter Aggressive Routability Optimizations to Always 4.2.4.3. Guideline: Increase Router Effort Multiplier 4.2.4.4. Guideline: Remove Fitter Constraints 4.2.4.5. Guideline: Optimize Synthesis for Routability 4.2.4.6. Guideline: Optimize Source Code 4.2.4.7. Guideline: Use a Larger Device
4.3. Scripting Support x
4.3.1. Initial Compilation Settings 4.3.2. Resource Utilization Optimization Techniques
5. Timing Closure and Optimization x
5.1. Optimize Multi Corner Timing 5.2. Optimize Critical Paths 5.3. Optimize Critical Chains 5.4. Design Evaluation for Timing Closure 5.5. Timing Optimization 5.6. Periphery to Core Register Placement and Routing Optimization 5.7. Scripting Support 5.8. Timing Closure and Optimization Revision History
5.2. Optimize Critical Paths x
5.2.1. Viewing Critical Paths
5.3. Optimize Critical Chains x
5.3.1. Viewing Critical Chains
5.4. Design Evaluation for Timing Closure x
5.4.1. Review Messages 5.4.2. Evaluate Fitter Netlist Optimizations 5.4.3. Evaluate Optimization Results 5.4.4. Evaluate Resource Usage 5.4.5. Evaluate Other Reports and Adjust Settings Accordingly 5.4.6. Evaluate Clustering Difficulty 5.4.7. Revise and Recompile
5.4.4. Evaluate Resource Usage x
5.4.4.1. Evaluate Global and Non-Global Usage 5.4.4.2. Evaluate Routing Usage 5.4.4.3. Evaluate Wires Added for Hold
5.5. Timing Optimization x
5.5.1. Correct Design Assistant Rule Violations 5.5.2. Implement Fast Forward Timing Closure Recommendations 5.5.3. Review Timing Path Details 5.5.4. Try Optional Fitter Settings 5.5.5. Back-Annotating Optimized Assignments 5.5.6. Optimize Settings with Design Space Explorer II 5.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard 5.5.8. I/O Timing Optimization Techniques 5.5.9. Register-to-Register Timing Optimization Techniques 5.5.10. Metastability Analysis and Optimization Techniques
5.5.2. Implement Fast Forward Timing Closure Recommendations x
5.5.2.1. Retiming Limit Details Report 5.5.2.2. Fast Forward Timing Closure Recommendations
5.5.2.1. Retiming Limit Details Report x
5.5.2.1.1. Using the Retiming Limit Details Report
5.5.2.2. Fast Forward Timing Closure Recommendations x
5.5.2.2.1. Generating Fast Forward Timing Closure Recommendations 5.5.2.2.2. Implementing Fast Forward Recommendations
5.5.3. Review Timing Path Details x
5.5.3.1. Report Timing 5.5.3.2. Report Logic Depth 5.5.3.3. Report Neighbor Paths 5.5.3.4. Report Register Spread 5.5.3.5. Report Route Net of Interest 5.5.3.6. Report Retiming Restrictions 5.5.3.7. Report Pipelining Information 5.5.3.8. Report CDC Viewer 5.5.3.9. Timing Closure Recommendations 5.5.3.10. Global Network Buffers 5.5.3.11. Resets and Global Networks 5.5.3.12. Suspicious Setup 5.5.3.13. Auto Shift Register Replacement 5.5.3.14. Clocking Architecture
5.5.3.4. Report Register Spread x
5.5.3.4.1. Understanding Report Register Spread Data
5.5.3.10. Global Network Buffers x
5.5.3.10.1. Source Location 5.5.3.10.2. Insertion Delay 5.5.3.10.3. Fan-Out 5.5.3.10.4. Global Signal Assignment
5.5.4. Try Optional Fitter Settings x
5.5.4.1. Optimize Hold Timing 5.5.4.2. Fitter Aggressive Routability Optimization
5.5.6. Optimize Settings with Design Space Explorer II x
5.5.6.1. Running DSE II Settings Exploration 5.5.6.2. Specifying DSE II Computing Resources 5.5.6.3. DSE II Optimization Parameters (Exploration Page) 5.5.6.4. Viewing DSE II Results
5.5.6.2. Specifying DSE II Computing Resources x
5.5.6.2.1. DSE II Setup Page Settings Compilation Type Settings Kubernetes Remote Farm Settings LSF Remote Settings PBSPro Remote Farm Settings Slurm Remote Farm Settings SunGrid (Beta) Remote Farm Settings Torque Remote Farm Settings
5.5.7. Aggregating and Comparing Compilation Results with Exploration Dashboard x
5.5.7.1. Aggregation Use Case 5.5.7.2. Comparison Use Case 5.5.7.3. Exploration Dashboard Object-Property Model 5.5.7.4. Starting the Exploration Dashboard
5.5.7.3. Exploration Dashboard Object-Property Model x
5.5.7.3.1. Base Exploration Dashboard Properties 5.5.7.3.2. Project Handle Properties 5.5.7.3.3. Project Group Objects and Properties 5.5.7.3.4. Workspace Objects and Properties
5.5.8. I/O Timing Optimization Techniques x
5.5.8.1. I/O Timing Constraints 5.5.8.2. Optimize IOC Register Placement for Timing Logic Option 5.5.8.3. Fast Input, Output, and Output Enable Registers 5.5.8.4. Programmable Delays 5.5.8.5. Use PLLs to Shift Clock Edges 5.5.8.6. Use Fast Regional Clock Networks and Regional Clocks Networks 5.5.8.7. Spine Clock Limitations
5.5.9. Register-to-Register Timing Optimization Techniques x
5.5.9.1. Optimize Source Code 5.5.9.2. Improving Register-to-Register Timing 5.5.9.3. Physical Synthesis Optimizations 5.5.9.4. Set Power Optimization During Synthesis to Normal Compilation 5.5.9.5. Optimize Synthesis for Performance, Not Area 5.5.9.6. Flatten the Hierarchy During Synthesis 5.5.9.7. Set the Synthesis Effort to High 5.5.9.8. Change Adder Tree Styles 5.5.9.9. Duplicate Registers for Fan-Out Control 5.5.9.10. Prevent Shift Register Inference 5.5.9.11. Use Other Synthesis Options Available in Your Synthesis Tool 5.5.9.12. Fitter Seed 5.5.9.13. Set Maximum Router Timing Optimization Level 5.5.9.14. Register-to-Register Timing Analysis
5.5.9.9. Duplicate Registers for Fan-Out Control x
5.5.9.9.1. Manual Register Duplication 5.5.9.9.2. Automatic Register Duplication: Estimated Physical Proximity 5.5.9.9.3. Automatic Register Duplication: Hierarchical Proximity
5.5.9.14. Register-to-Register Timing Analysis x
5.5.9.14.1. Tips for Analyzing Failing Paths 5.5.9.14.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains 5.5.9.14.3. Tips for Critical Path Analysis 5.5.9.14.4. Tips for Creating a .tcl Script to Monitor Critical Paths Across Compiles 5.5.9.14.5. Global Routing Resources 5.5.9.14.6. Register RAMS and DSPs
5.6. Periphery to Core Register Placement and Routing Optimization x
5.6.1. Setting Periphery to Core Optimizations in the Advanced Fitter Setting Dialog Box 5.6.2. Setting Periphery to Core Optimizations in the Assignment Editor 5.6.3. Viewing Periphery to Core Optimizations in the Fitter Report
5.7. Scripting Support x
5.7.1. Initial Compilation Settings 5.7.2. I/O Timing Optimization Techniques 5.7.3. Register-to-Register Timing Optimization Techniques
6. Analyzing and Optimizing the Design Floorplan x
6.1. Location Assignment Optimization Guidelines 6.2. Design Floorplan Analysis in Chip Planner 6.3. Defining Logic Lock Placement Constraints 6.4. Defining Virtual Pins 6.5. Using Logic Lock Regions in Combination with Design Partitions 6.6. Creating Clock Region Assignments in Chip Planner 6.7. Scripting Support 6.8. Analyzing and Optimizing the Design Floorplan Revision History
6.2. Design Floorplan Analysis in Chip Planner x
6.2.1. Starting the Chip Planner 6.2.2. Chip Planner GUI 6.2.3. Viewing Design Elements in Chip Planner 6.2.4. Finding Design Elements in the Chip Planner 6.2.5. Exploring Paths in the Chip Planner 6.2.6. Viewing Assignments in the Chip Planner 6.2.7. Viewing High-Speed and Low-Power Tiles in the Chip Planner 6.2.8. Viewing Design Partition Placement
6.2.3. Viewing Design Elements in Chip Planner x
6.2.3.1. Viewing Architecture-Specific Design Information in Chip Planner 6.2.3.2. Viewing Available Clock Networks in Chip Planner 6.2.3.3. Viewing Clock Sector Utilization in Chip Planner 6.2.3.4. Viewing Routing Congestion in Chip Planner 6.2.3.5. Viewing I/O Banks in Chip Planner 6.2.3.6. Viewing High-Speed Serial Interfaces (HSSI) in Chip Planner 6.2.3.7. Viewing Source and Destination Nodes in Chip Planner 6.2.3.8. Viewing Fan-In and Fan-Out in Chip Planner 6.2.3.9. Viewing Immediate Fan-In and Fan-Out in Chip Planner 6.2.3.10. Viewing the Selected Contents in Chip Planner 6.2.3.11. Viewing the Location and Utilization of Device Resources in Chip Planner 6.2.3.12. Viewing Module Placement by Cross-Probing to Chip Planner
6.2.3.4. Viewing Routing Congestion in Chip Planner x
6.2.3.4.1. Areas with Routing Congestion 6.2.3.4.2. Congestion due to HDL Coding style
6.2.4. Finding Design Elements in the Chip Planner x
6.2.4.1. Find Options (Chip Planner Search)
6.2.5. Exploring Paths in the Chip Planner x
6.2.5.1. Analyzing Connections for a Path 6.2.5.2. Locate Path from the Timing Analysis Report to the Chip Planner 6.2.5.3. Show Delays 6.2.5.4. Viewing Routing Resources
6.3. Defining Logic Lock Placement Constraints x
6.3.1. The Logic Lock Regions Window 6.3.2. Defining Logic Lock Regions 6.3.3. Customizing the Shape of Logic Lock Regions 6.3.4. Assigning Device Pins to Logic Lock Regions 6.3.5. Viewing Connections Between Logic Lock Regions in Chip Planner 6.3.6. Example: Placement Best Practices for Arria® 10 FPGAs 6.3.7. Migrating Assignments between Quartus® Prime Standard Edition and Quartus® Prime Pro Edition
6.3.2. Defining Logic Lock Regions x
6.3.2.1. Defining a Logic Lock Region in Chip Planner 6.3.2.2. Defining a Logic Lock Region from the Project Navigator 6.3.2.3. Defining Routing Regions 6.3.2.4. Defining Empty Logic Lock Regions 6.3.2.5. Defining Hierarchical Logic Lock Regions
6.3.2.1. Defining a Logic Lock Region in Chip Planner x
6.3.2.1.1. Logic Lock Region Properties 6.3.2.1.2. Snapping to a Region 6.3.2.1.3. Considerations for Auto Sized Regions
6.3.3. Customizing the Shape of Logic Lock Regions x
6.3.3.1. Adding a New Shape to a Logic Lock Region 6.3.3.2. Subtracting Shape from Logic Lock Region 6.3.3.3. Merging Logic Lock Regions 6.3.3.4. Defining Noncontiguous Logic Lock Regions
6.5. Using Logic Lock Regions in Combination with Design Partitions x
6.5.1. Viewing Design Connectivity and Hierarchy
6.6. Creating Clock Region Assignments in Chip Planner x
6.6.1. Creating Clock Assignments in Chip Planner 6.6.2. Resizing a Clock Assignment in Chip Planner 6.6.3. Moving a Clock Assignment in Chip Planner 6.6.4. Deleting a Clock Region Assignment in Chip Planner 6.6.5. Assigning a Clock Signal to a Clock Region in Chip Planner
6.6.1. Creating Clock Assignments in Chip Planner x
6.6.1.1. Clock Assignment Properties
6.7. Scripting Support x
6.7.1. Creating Logic Lock Assignments with Tcl commands 6.7.2. Assigning Virtual Pins with a Tcl command 6.7.3. Logic Lock Region Assignment Examples
7. Using the ECO Compilation Flow x
7.1. ECO Compilation Flow 7.2. ECO Tcl Script Example 7.3. Viewing ECO Compilation Reports 7.4. ECO Commands 7.5. ECO Command Limitations 7.6. Interactive ECO Fitting 7.7. Using the ECO Compilation Flow Revision History
7.4. ECO Commands x
7.4.1. ECO Command Quick Reference 7.4.2. make_connection 7.4.3. remove_connection 7.4.4. modify_lutmask 7.4.5. adjust_pll_refclk 7.4.6. modify_io_slew_rate 7.4.7. modify_io_current_strength 7.4.8. modify_io_delay_chain 7.4.9. create_new_node 7.4.10. remove_node 7.4.11. place_node 7.4.12. unplace_node 7.4.13. create_wirelut
7.6. Interactive ECO Fitting x
7.6.1. eco_load_design and eco_commit_design Commands
Answers to Top FAQs
1. Design Optimization Overview
2. Optimizing the Design Netlist
3. Netlist Optimizations and Physical Synthesis
4. Area Optimization
5. Timing Closure and Optimization
6. Analyzing and Optimizing the Design Floorplan
7. Using the ECO Compilation Flow
8. Quartus® Prime Pro Edition Design Optimization User Guide Archives
A. Quartus® Prime Pro Edition User Guides

5.5.6.2.1. DSE II Setup Page Settings

DSE II provides the following options for configuring your DSE II setup:

Compilation Type Settings

Choose one of the following options for specifying the type of computing resources to use for DSE II compilation processing. DSE II supports parallel processing, allowing you to distribute the multi-compilation workload across distributed remote resources.

Table 27.  Compilation Type Settings
Compilation Type Description
Local Compile from the host machine.
Remote
The available options are:
Kubernetes (beta)
LSF
PBSPro
Slurm
SSH
SunGrid (Beta)
Torque

Kubernetes Remote Farm Settings

The following settings are available for this option.

Table 28.  Kubernetes Remote Farm Settings
Parameter Comments
Remote Cluster (Beta) Specify on if the machine is outside of the Kubernetes cluster and does not share a network. This option is a beta feature in the current release.1
Service Account Name Specifies the Kubernetes Service Account to use. This account needs to enable permissions verbs create, get, and delete on jobs, pods, pods/log and events. DSE II can create a new Service Account with required permissions if you do not specify one, but this requires that you already have rbac.authorization.k8s.io/v1 API access.2
Create Service Account Specify on to create a new Kubernetes Service Account with the name quartus-dse on the specified namespace or default namespace. Create quartus-dse role to allow verbs create, get, and delete on jobs, pods, pods/log and events. Bind this role to the quartus-dse service account.
Full path to kubectl Specifies the full path to the kubectl executable. The default value is kubectl and assumes is the PATH.
Kubeconfig File Specifies the kubeconfig file that you use to login to the Kubernetes cluster.
Namespace Specifies the Kubernetes cluster namespace that you are operating in.
CPU limit Specifies as decimal value a limit on the number of CPUs that you use. Default value is 2.
CPU Request Specifies as decimal value the number of CPUs that you require. Default value is 2. A lower number schedules a job. Once assigned to node, if more CPU resources are available, DSE II uses up to the CPU limit.
Set environment variables Accepts a comma separated list of name=value pairs.
Memory limit Specifies the memory limit as <value><unit>. Units can be Gi and Mi. Example is 32Gi.
Memory request Specifies the memory that you want to request as <value><unit>. Units can be Gi and Mi. Example is 32Gi. If more memory resources are available, DSE II uses up to the Memory limit.
Pull image before running Accepts string of Always, IfNotPresent, Never. Default value is ifNotPresent.
Container image Specifies the container image with the Quartus® Prime software installation. For example:
altera/quartuspro-v25.1
Only run on a specific node Specifies the node that you want to run DSE II exploration.
Select the nodes to run based on node label Specifies the node label to use the node. For example, mylabel = myteam
LM_LICENSE_FILE Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting.
Initial Work Directory Specifies the initial directory for the remote job. For example:
/data/user/my_project
Active Deadline Seconds Specifies in seconds a time limit the job is allowed to work. The job terminates unless it finishes in the time you specify. Default value is 86400 seconds (24 hours).
Time to live after finished Specifies in seconds the time job is allowed to remain in Kubernetes after the job finishes. The TTL control cleans up the job if you specify a time.
Do not delete pod Specify on to prevent deletion of the pod from the cluster after it terminates. You can use this option to diagnose problems.
Keep Manifest Files Specifies on to retain the Kubernetes manifest .json files that DSE II creates. You can use this option to diagnose problems.
Additional Remote Settings Optional field for other Kubernetes remote settings.

LSF Remote Settings

The following settings are available for this option:

Table 29.  LSF Remote Farm Settings
Parameter Comments
Resource Requirements

Specify memory requirements for the machines that run jobs. Example:

"rusage[mem=1000]" (including quotes) * Require 1000 MB RAM for submitted jobs.
Queues One or more comma-separated queues.
Quartus Root Directory Specifies the Quartus® Prime software installation location. For example:
/altera/25.1/quartus
LM_LICENSE_FILE Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting.
Initial Work Directory Specifies the initial directory for the remote job. For example:
/data/user/my_project
Environment Variables Specifies options to control environment propagation and specific environment variables. For example:
all, 
PATH=/acds/25.1/linux64/quartus/bin:%PATH%
Local to Remote Path Mapping Specifies the shared directory mapping between the local and remote host. Use format localpath;remote_path. Windows to Linux example:
[drive:\windows path];[linux path]
s:\designs\two_reg;/designs/two_reg
Priority Sets the job priority level from 0 (lowest priority) to 300 (highest priority). Default value is 150.
Standard Output File Specifies the file to store standard output. You can include Job ID using %J or Index ID using %I in the directory or filename.
Error Output File Specifies the file to store standard error output. You can include Job ID using %J or Index ID using %I in the directory or filename.
Processor Limits Specifies the minimum number of processors, and optionally the maximum number of processors for the job. For example, specifying 2 sets a minimum number of two processors. Specifying 3,5 sets a minimum of three and a maximum of five processors.
Additional remote settings Specify other settings

PBSPro Remote Farm Settings

The following settings are available for this option:

Table 30.  PBSPro Remote Farm Settings
Parameter Comments
Queues Specifies the name of the job you that you want to use.
Priority Sets the job priority level from -1024 (lowest priority) to 1024 (highest priority).
Resource, Architecture, Memory Requirement Specifies the architecture, license, or memory requirements for the job. For example: 
select=mem=16gb:ncpus=4
Email Specifies a comma separated list of email addresses to receive status emails.
Additional Arguments to qsub Optional field for other qsub remote settings.
Quartus Root Directory Specifies the Quartus® Prime software installation location. For example:
/altera/25.1/quartus
LM_LICENSE_FILE Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting.
Environment Variables Specifies a comma separated list of environment variables to pass to the job. Enclose values with single or double quote if it includes a comma. For example:a=1, b='ab", c=3.
Initial Work Directory Specifies the initial directory for the remote job. For example:
/data/user/my_project

Slurm Remote Farm Settings

The following settings are available for this option:

Table 31.  Slurm Remote Farm Settings
Parameter Comments
Cluster Specifies a comma separate list of clusters to use for the job.
Partition Specifies a comma separate list of partitions to use for the job.
Memory per Node Specifies the architecture, license, or memory requirements for the job. For example: 
select=mem=16gb:ncpus=4
CPUs per task Specifies the maximum number of CPUs to use for each task.
CPU Sockets per Node Specifies the maximum number of CPUs to use for each node.
CPU Cores per Sockets Specifies the maximum number of CPU cores to use for each socket.
Priority Specifies the job priority as numeric value or TOP to specify highest priority possible. Highest value numbers are highest priority.
Generic resources Specifies the architecture, license, or memory requirements for the job. For example: 
select=mem=16gb:ncpus=4
Constraint Specifies node features as required by Slurm administrator.
Modules Specifies command separated list of modules. A module configures one or more environment settings. One of the modules must configure the QUARTUS_ROOTDIR and add the Quartus® Prime software to the PATH.
Email Specifies a comma separated list of email addresses to receive status emails.
Additional Arguments to sbatch Optional field for specifying additional options for Slurm.
Quartus Root Directory Specifies the Quartus® Prime software installation location. For example:
/altera/25.1/quartus
LM_LICENSE_FILE Specifies the LM_LICENSE_FILE environment setting. Default value is the current local setting.
Environment Variables Specifies a comma separated list of environment variables to pass to the job. Enclose values with single or double quote if it includes a comma. For example:a=1, b='ab", c=3.
Initial Work Directory Specifies the initial directory for the remote job. For example:
/data/user/my_project
Standard Output File Specifies the file to store standard output. You can include Job ID using %J or Index ID using %I in the directory or filename.
Licenses Specifies the path to any required licenses for the job.

SunGrid (Beta) Remote Farm Settings

The following settings are available for this option:

Table 32.  SunGrid Remote Farm Settings
Parameter Comments
Environment Variables Specifies a comma separated list of environment variables to pass to the job. For example, DEBUG=1, SIZE=LARGE.
Queues Specifies the name of the job you that you want to use.
Priority Sets the job priority level from -1024 (lowest priority) to 1024 (highest priority).
Resource, Architecture, Memory Requirement Specifies the architecture, license, or memory requirements for the job. For example: 
h_vmem=750M, h_cpu=0:45:0
uses a machine with minimum of 750M and runs job no longer than 45 minutes.
Email Specifies a comma separated list of email addresses to receive status emails.
Parallel Processor Specifies the minimum number of processors, and optionally the maximum number of processors for the job. For example, specifying 4-16 sets a minimum number of four processors and a maximum of 16 processors.
Additional remote settings Specify other settings

Torque Remote Farm Settings

The following settings are available for this option:

Table 33.  Torque Remote Farm Settings
Parameter Comments
Environment Variables Specifies a comma separated list of environment variables to pass to the job. For example, DEBUG=1, SIZE=LARGE.
Queues Specifies the name of the job you that you want to use.
Priority Sets the job priority level from -1024 (lowest priority) to 1024 (highest priority).
Resource, Architecture, Memory Requirement Specifies the architecture, license, or memory requirements for the job. For example: 
h_vmem=750M, h_cpu=0:45:0
uses a machine with minimum of 750M and runs job no longer than 45 minutes.
Email Specifies a comma separated list of email addresses to receive status emails.
Additional Arguments to qsub Specifies any additional arguments.
Additional remote settings Specify other settings
1 This is a beta feature in this version of the Quartus® Prime software.
2 The Quartus® Prime software includes a service account template at: /quartus/common/python/lib/site-packages/quartus/dse/plugins/farms/ kube_job_serviceaccount_template.json for cluster admin to review, copy, and revise with the actual namespace. You can then create it using: kubectl --namespace <namespace> apply -f <serviceaccount.json>. For Kubernetes service account information, refer to https://kubernetes.io/docs/concepts/security/service-accounts/.
Level Two Title