Nios® V Processor Reference Manual

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ID 683632
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. About this Document 2. Nios® V/m Processor 3. Document Revision History for the Nios® V Processor Reference Manual
1. About this Document x
1.1. Overview
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Control and Status Registers 2.3.4. Exception Controller 2.3.5. Interrupt Controller 2.3.6. Memory and I/O Organization 2.3.7. RISC-V based Debug Module
2.3.5. Interrupt Controller x
2.3.5.1. Timer and Software Interrupt Module
2.3.6. Memory and I/O Organization x
2.3.6.1. Instruction and Data Buses
2.3.6.1. Instruction and Data Buses x
2.3.6.1.1. Instruction Manager Port 2.3.6.1.2. Data Manager Port 2.3.6.1.3. Address Map
2.3.7. RISC-V based Debug Module x
2.3.7.1. Debug Mode 2.3.7.2. Halt from Debug Module 2.3.7.3. Debug Implementation 2.3.7.4. Abstract Commands in Debug Mode 2.3.7.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. About this Document
2. Nios® V/m Processor
3. Document Revision History for the Nios® V Processor Reference Manual

2.4.2. Control and Status Registers (CSR) Mapping

Control and status registers report the status and change the behavior of the processor. Since the processor core only supports M-mode and D-mode, Nios® V/m processor implements the CSRs supported by these two modes.

Table 13.  Control and Status Registers List
Number Privilege Name Description
Machine Information Register
0xF11 MRO mvendorid Vendor ID. Refer to .
0xF12 MRO marchid Architecture ID. Refer to .
0xF13 MRO mimpid Implementation ID. Refer to .
0xF14 MRO mhartid Hardware thread ID. Refer to .
Machine Trap Setup
0x300 MRW mstatus Machine status register. Refer to .
0x301 MRW misa ISA and extensions. Refer to .
0x304 MRW mie Machine interrupt-enable register. Refer to .
0x305 MRW mtvec Machine trap-handler base address. Refer to .
Machine Trap Handling
0x341 MRW mepc Machine exception program counter. Refer to .
0x342 MRW mcause Machine trap cause. Refer to .
0x343 MRW mtval Machine bad address or instruction. Refer to .
0x344 MRW mip Machine interrupt pending. Refer to .
Debug Mode Registers
0x7B0 DRW dcsr Debug control and status register. Refer to .
0x7B1 DRW dpc Debug Program Counter. Refer to .
Related Information
Level Two Title