F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 8/04/2023
Public
Document Table of Contents

4.1.2.1. Receive Path Blocks

The Interlaken IP core receive data path has the following four main functional blocks:
  • RX PMA
  • RX PCS
  • RX MAC
  • RX Regroup Block
The Interlaken IP core receive data path has the following four main functional blocks:
  • RX PMA
  • RX PCS
  • RX MAC
  • RX Regroup Block

RX PMA

The Interlaken IP core RX PMA deserializes data that the IP core receives on the serial lines of the Interlaken link. The RX PMA contains RS FEC block in PAM4 mode of E-tile devices and three RS FEC (544,514) blocks in 6x 53.125 Gbps PAM4 mode configuration. Each RS FEC block serves four FEC channels in the aggregate mode.

RX PCS

The FPGA soft logic implements RX PCS. In PAM4 mode, the IP core contains a soft logic transcoder block to work with RS FEC of the RX PMA. The Interlaken IP core RX PCS block performs the following functions to retrieve the data:
  • Detects word lock and word synchronization.
  • Checks running disparity.
  • Reverses gear-boxing and 64/67B encoding.
  • Descrambles the data.
  • Delineates meta frame boundaries.
  • Performs CRC32 checking.
  • Sends lane status information to the calendar and status blocks, if Include in-band flow control functionality is turned on.
  • Performs asynchronous operations and receiver alignment using RX Align FIFO.
  • Performs the Interlaken inverse transcoding function on the data received from the RX RS FEC (544, 514) in PAM4 mode IP variations.

RX MAC

To recover a packet or burst, the RX MAC takes data from each of the PCS lanes and reassembles the packet or burst. The Interlaken IP core RX MAC performs the following functions:
  • Data de-striping, including lane alignment and burst assembly from the PCS lanes.
  • CRC24 validation.
  • Calendar recovery, if Include in-band flow control functionality is turned on.

RX Regroup Block

The Interlaken IP core RX regroup block translates the IP core internal data format to the outgoing user application data irx_dout_words format.

For details on transceiver initialization, please refer to the F-Tile Architecture PHY IP User Guide.

Did you find the information on this page useful?

Characters remaining:

Feedback Message