Ethernet Design Example Components Release Notes

Download PDF
ID 683598
Date 5/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. Ethernet Design Example Components Release Notes
1. Ethernet Design Example Components Release Notes x
1.1. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP 1.2. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP 1.3. Ethernet Packet Classifier Intel® FPGA IP 1.4. Ethernet Design Example Components v17.0 1.5. Ethernet Design Example Components v16.0 1.6. Ethernet Design Example Components User Guide Archives
1.1. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP x
1.1.1. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v20.1.2 1.1.2. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v20.1.1 1.1.3. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v20.0.0 1.1.4. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v19.3.0 1.1.5. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v19.2.0 1.1.6. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v18.0 1.1.7. Ethernet IEEE 1588 Time of Day Clock Intel® FPGA IP v17.1
1.2. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP x
1.2.1. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.6 1.2.2. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.5 1.2.3. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.4 1.2.4. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.0 1.2.5. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v19.2.0 1.2.6. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v18.0 1.2.7. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v17.1
1.3. Ethernet Packet Classifier Intel® FPGA IP x
1.3.1. Ethernet Packet Classifier Intel® FPGA IP v19.3.3 1.3.2. Ethernet Packet Classifier Intel® FPGA IP v19.3.1 1.3.3. Ethernet Packet Classifier Intel® FPGA IP v18.0
1. Ethernet Design Example Components Release Notes

1.2.3. Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP v20.0.4

Table 10.  v20.0.4 2023.12.04
Quartus® Prime Version Description Impact
23.4 Ethernet IEEE 1588 TOD Synchronizer Intel® FPGA IP has lower timing margin for Agilex™ 7 I-Series OPNs with device density code of 041. —
Level Two Title