eCPRI Intel® FPGA IP Release Notes

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ID 683570
Date 8/03/2023
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1. eCPRI Intel® FPGA IP Release Notes
1. eCPRI Intel® FPGA IP Release Notes x
1.1. eCPRI Intel® FPGA IP v2.0.4 1.2. eCPRI Intel® FPGA IP v2.0.3 1.3. eCPRI Intel® FPGA IP v2.0.1 1.4. eCPRI Intel® FPGA IP v2.0.0 1.5. eCPRI Intel® FPGA IP v1.4.1 1.6. eCPRI Intel® FPGA IP v1.4.0 1.7. eCPRI Intel® FPGA IP v1.3.0 1.8. eCPRI Intel® FPGA IP v1.2.0 1.9. eCPRI Intel® FPGA IP v1.1.0 1.10. eCPRI Intel® FPGA IP v1.0.0 1.11. eCPRI Intel FPGA IP User Guide Archives 1.12. eCPRI Intel® FPGA IP Design Example User Guide Archives
1. eCPRI Intel® FPGA IP Release Notes

1.8. eCPRI Intel® FPGA IP v1.2.0

Table 8.  v1.2.0 2021.01.08
Intel® Quartus® Prime Version Description Impact
20.3 Added support for interworking function (IWF) type 0. You can connect eCPRI node with one CPRI node.
Supports pairing of eCPRI Intel FPGA IP with O-RAN Intel FPGA IP. —
Added following new IWF related parameters:
  • Interworking Function (IWF) Support
  • Interworking Function (IWF) Type
  • Interworking Function (IWF) Number of CPRI
Using these parameters, you can enable your eCPRI IP for IWF functionality.
Added following IWF related interfaces:
  • IWF Type 0 eCPRI Source Interface
  • IWF Type 0 eCPRI Sink Interface
  • IWF Type 0 CPRI MAC Interface
Note: Refer to eCPRI Intel FPGA IP User Guide for detailed information on signals related to these interfaces.
—
Added following clock signals:
  • iwf_gmii_rxclk[N]
  • iwf_gmii_txclk[N]
  • gmii_rxclk[N]
  • gmii_txclk[N]
—
Added following reset signals:
  • iwf_rst_tx_n
  • iwf_rst_rx_n
  • rst_tx_n_sync
  • rst_rx_n_sync
  • iwf_gmii_rxreset_n[N]
  • iwf_gmii_txreset_n[N]
  • gmii_rxreset_n[N]
  • gmii_txreset_n[N]
—
The eCPRI IP design example for Intel® Arria® 10 device is now available. —
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