R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 6/26/2023

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Document Table of Contents

4. Document Revision History for the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.06.26 23.2 10.0.0

Changed the Intel® Quartus® Prime version number and IP version number.

2023.04.03 23.1 9.0.0
  • Updated product family name to "Intel Agilex® 7"
  • Added a new section Functional Description for the Performance Design Example
  • Added a new section Running the Performance Design Example
2022.12.19 22.4 8.0.0 Updated the ACDS version number and the IP version number.
2022.09.26 22.3 7.0.0
  • Added the section Functional Description for the Single Root I/O Virtualization (SR-IOV) Design Example.
  • Added steps to generate the SR-IOV design example to the section Generating the Design Example.
  • Added the section SR-IOV Design Example Testbench.
  • Added the section Running the SR-IOV Design Example.
2022.06.20 22.2 6.0.0 Added a section on how to simulate the design example using the Xcelium* simulator.
2022.03.28 22.1 5.0.0
  • Added a summary table of all the configurations supported by this design example to the Design Example Description section.
  • Added the Hardware and Software Requirements section.
  • Updated the Simulating the Design Example section to include clearer instructions on how to simulate the design example using various simulators.
2021.12.13 21.4 4.0.0 Added support for the Gen4 x16, Gen3 x16, Gen4 2x8 and Gen3 2x8 design examples.
2021.10.04 21.3 3.0.0 Added instructions on how to simulate the design example using the VCS* MX simulator to the section Simulating the Design Example.
2021.07.12 21.2 2.0.0 Initial release.