AN 917: Reset Design Techniques for Hyperflex® Architecture FPGAs

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ID 683539
Date 7/07/2025
Public
Document Table of Contents
Document Table of Contents x
1. AN 917: Reset Design Techniques for Hyperflex® Architecture FPGAs
1. AN 917: Reset Design Techniques for Hyperflex® Architecture FPGAs x
1.1. General Reset Recommendations 1.2. Reset Design Strategies 1.3. Analyzing Resets with Design Assistant 1.4. Implementing Reset Circuitry 1.5. Document Revision History for AN 917: Reset Design Techniques for Hyperflex® Architecture FPGAs
1.1. General Reset Recommendations x
1.1.1. Limit Reset Usage 1.1.2. Hyper-Registers Require Synchronous Reset
1.2. Reset Design Strategies x
1.2.1. Asynchronous Reset Design Strategies 1.2.2. Synchronous Reset Design Strategies
1.2.1. Asynchronous Reset Design Strategies x
1.2.1.1. Recovery and Removal Checks
1.3. Analyzing Resets with Design Assistant x
1.3.1. Example: Asynchronous Reset Design Assistant Analysis 1.3.2. Example: Synchronous Reset Design Assistant Analysis
1.3.1. Example: Asynchronous Reset Design Assistant Analysis x
1.3.1.1. Adding SDC Constraints to Asynchronous Reset Circuitry
1.4. Implementing Reset Circuitry x
1.4.1. Reset Coding Techniques 1.4.2. Avoiding Common Reset Coding Issues 1.4.3. Generating Synchronous Reset Trees 1.4.4. Reset Removal on Multi Clock Domain Designs 1.4.5. Using the Reset Release IP 1.4.6. Adding Clock Cycles to the Reset Sequence
1.4.1. Reset Coding Techniques x
1.4.1.1. Converting to Synchronous Resets
1.4.2. Avoiding Common Reset Coding Issues x
1.4.2.1. Coding Synchronous Reset with Follower Registers 1.4.2.2. Coding Reset-Related Optimizations
1.4.3. Generating Synchronous Reset Trees x
1.4.3.1. Reset Distribution through Hyper-Pipelining and Hyper-Retiming 1.4.3.2. Adding Pipeline Registers and Automatic Register Duplication
1.4.6. Adding Clock Cycles to the Reset Sequence x
1.4.6.1. C-Cycle Equivalence 1.4.6.2. Determining the Reset Sequence Requirement
1. AN 917: Reset Design Techniques for Hyperflex® Architecture FPGAs

1. AN 917: Reset Design Techniques for Hyperflex® Architecture FPGAs

Updated for:
Intel® Quartus® Prime Design Suite 25.1.1

This document describes reset design techniques to ensure reliable power-up, reset release conditions, and maximum performance on Hyperflex® architecture FPGAs. Proper application of reset design techniques allows you to take full advantage of the Hyper-Pipelining and Hyper-Retiming performance optimization features in Stratix® 10 and Agilex™ FPGA portfolio devices (Agilex 7, Agilex™ 5, and Agilex™ 3).

Refer to the following reset recommendations, strategies, and recommended coding techniques for effective reset implementation:


Section Content
General Reset Recommendations
Reset Design Strategies
Analyzing Resets with Design Assistant
Implementing Reset Circuitry
Document Revision History for AN 917: Reset Design Techniques for Hyperflex Architecture FPGAs

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