AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel Stratix 10 Devices

Download PDF
ID 683529
Date 5/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B IP Core and ADC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 832: Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Receiver Data Link Layer 1.3.2. Receiver Transport Layer 1.3.3. Descrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Receiver Data Link Layer x
1.3.1.1. Code Group Synchronization (CGS) 1.3.1.2. Initial Frame and Lane Synchronization (ILA)
1. Intel FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Intel® Stratix® 10 Devices

1.8. Appendix

Device Used and Quartus Tool Version

For interoperability with ADC AD9208, two device variants of Intel® Stratix® 10 are used.

  • For lane rates above 15G and up to 16G: 1SG280HU1F50E1VGS1 (Transceiver speed grade -1 device)
  • For lane rates of 15G and lower: 1SG280HU2F50E2VGS1 (Transceiver speed grade -2 device)

Except for the modes LMF 821/822/841/842, these modes were generated in Transceiver speed grade -1 device in order to achieve timing.

Intel® Quartus® Prime Pro Edition software version 17.1 IR2 Build 50 is used for compilation of designs.

Timing Closure Details

To achieve timing closure, the I/O ports of Assembler (Assembler to JESD IP) & De-assembler (JESD IP to De-assembler) were pipelined for the test modes LMF 882 & 884.

Synthesis/Fitter Settings:

The following Analysis/Fitter settings were added to the qsf file to close the timing requirements for the variants LMF 882 & LMF 884.

Compiler Setting Value Used Default Value
Optimization Technique Speed Balanced
Optimization Mode Aggressive Balanced
Router Timing Optimization Level Maximum Normal
Auto Packed Registers Normal Auto
Physical Synthesis ON OFF
Restructure Multipliers OFF Auto
Fitter Initial Placement Seed 1-10 1
Additional JESD modes supported by ADC:

The modes enlisted here have not been validated in this interoperability test, but they are supported by the ADC. These have been tabulated here for future reference.

L M F S N N' Comments
1 8 16 1 14 16 F=16 configuration is not supported by transport layer of Intel FPGA example design.
1 1 1 1 8 8

N’=8 configuration is not supported by transport layer of Intel FPGA example design.

1 1 2 2 8 8
2 1 1 2 8 8
2 1 2 4 8 8
2 1 4 8 8 8
4 1 1 4 8 8
4 1 2 8 8 8
1 2 2 1 8 8
2 2 1 1 8 8
2 2 2 2 8 8
4 2 1 2 8 8
4 2 2 4 8 8
4 2 4 8 8 8
Level Two Title