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1. Datasheet
2. Getting Started with the Cyclone V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History
1.1. Cyclone V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Clock Signals
4.2. Reset, Status, and Link Training Signals
4.3. ECRC Forwarding
4.4. Error Signals
4.5. Interrupts for Endpoints
4.6. Interrupts for Root Ports
4.7. Completion Side Band Signals
4.8. LMI Signals
4.9. Transaction Layer Configuration Space Signals
4.10. Hard IP Reconfiguration Interface
4.11. Power Management Signals
4.12. Physical Layer Interface Signals
15.6.1. ebfm_barwr Procedure
15.6.2. ebfm_barwr_imm Procedure
15.6.3. ebfm_barrd_wait Procedure
15.6.4. ebfm_barrd_nowt Procedure
15.6.5. ebfm_cfgwr_imm_wait Procedure
15.6.6. ebfm_cfgwr_imm_nowt Procedure
15.6.7. ebfm_cfgrd_wait Procedure
15.6.8. ebfm_cfgrd_nowt Procedure
15.6.9. BFM Configuration Procedures
15.6.10. BFM Shared Memory Access Procedures
15.6.11. BFM Log and Message Procedures
15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation
15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
15.7.3. Viewing the Important PIPE Interface Signals
15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
15.7.6. Changing between the Hard and Soft Reset Controller
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15.6.11.3. ebfm_log_set_suppressed_msg_mask Task
The ebfm_log_set_suppressed_msg_mask procedure controls which message types are suppressed.
Location |
altpcietb_bfm_driver_rp.v |
|
---|---|---|
Syntax |
ebfm_log_set_suppressed_msg_mask (msg_mask) |
|
Argument |
msg_mask | This argument is reg [EBFM_MSG_ERROR_CONTINUE: EBFM_MSG_DEBUG]. A 1 in a specific bit position of the msg_mask causes messages of the type corresponding to the bit position to be suppressed. |