Visible to Intel only — GUID: nik1410564773337
Ixiasoft
1. Datasheet
2. Getting Started with the Cyclone V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Frequently Asked Questions for PCI Express
B. Lane Initialization and Reversal
C. Document Revision History
1.1. Cyclone V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Clock Signals
4.2. Reset, Status, and Link Training Signals
4.3. ECRC Forwarding
4.4. Error Signals
4.5. Interrupts for Endpoints
4.6. Interrupts for Root Ports
4.7. Completion Side Band Signals
4.8. LMI Signals
4.9. Transaction Layer Configuration Space Signals
4.10. Hard IP Reconfiguration Interface
4.11. Power Management Signals
4.12. Physical Layer Interface Signals
15.6.1. ebfm_barwr Procedure
15.6.2. ebfm_barwr_imm Procedure
15.6.3. ebfm_barrd_wait Procedure
15.6.4. ebfm_barrd_nowt Procedure
15.6.5. ebfm_cfgwr_imm_wait Procedure
15.6.6. ebfm_cfgwr_imm_nowt Procedure
15.6.7. ebfm_cfgrd_wait Procedure
15.6.8. ebfm_cfgrd_nowt Procedure
15.6.9. BFM Configuration Procedures
15.6.10. BFM Shared Memory Access Procedures
15.6.11. BFM Log and Message Procedures
15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation
15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
15.7.3. Viewing the Important PIPE Interface Signals
15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
15.7.6. Changing between the Hard and Soft Reset Controller
Visible to Intel only — GUID: nik1410564773337
Ixiasoft
1.5. Configurations
The Cyclone V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:
- Physical (PHY), including:
- Physical Media Attachment (PMA)
- Physical Coding Sublayer (PCS)
- Media Access Control (MAC)
- Data Link Layer (DL)
- Transaction Layer (TL)
The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Intel devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You can customize the Hard IP to meet your design requirements.
Figure 2. PCI Express Application with a Single Root Port and EndpointThe following figure shows a PCI Express link between two Cyclone V FPGAs. One is configured as a Root Port and the other as an Endpoint.
Figure 3. PCI Express Application with an Endpoint Using the Multi-Function CapabilityThe following figure shows a PCI Express link between two Intel FPGAs. One is configured as a Root Port and the other as a multi-function Endpoint. The FPGA serves as a custom I/O hub for the host CPU. In the Cyclone V FPGA, each peripheral is treated as a function with its own set of Configuration Space registers. Eight multiplexed functions operate using a single PCI Express link.
Figure 4. PCI Express Application Using Configuration via Protocol The Cyclone V design below includes the following components:
- A Root Port that connects directly to a second FPGA that includes an Endpoint.
- Two Endpoints that connect to a PCIe switch.
- A host CPU that implements CvP using the PCI Express link connects through the switch. For more information about configuration over a PCI Express link below.
Related Information