Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide

ID 683510
Date 9/26/2022
Public Command Interface

Use the Avalon® Streaming ( Avalon® ST) interface to send commands to the SDM.
Table 3.  Command Interface
Signal Name Direction Description
command_ready Output The Mailbox Client with Avalon® ST Intel® FPGA IP asserts command_ready when it is ready to receive commands from the application. The ready_latency is 0 cycles. The Mailbox Client with Avalon® ST can accept command_data[31:0] in the same cycle that command_ready asserts.
command_valid Input The command_valid signal asserts to indicate that command_data is valid.
command_data[31:0] Input The command_data bus drives commands to the SDM. Refer to Command List and Description for definitions of the commands.
command_startofpacket Input The command_startofpacket asserts in the first cycle of a command packet.
command_endofpacket Input The command_endofpacket asserts in the last cycle of command a packet.
Figure 4. Timing for Avalon® ST Command Packet

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