Nios® II and Embedded IP Release Notes

ID 683482
Date 6/21/2022
Public

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4. Embedded IP Cores

Table 5.  Release Information for Embedded IP Cores
Intel® Quartus® Prime Software Version Key Updates
22.2 Added a new ECC option to the On-Chip Memory II (RAM or ROM) component.
22.1
  • Added support for a new IP core in Intel® Quartus® Prime: Cache Coherency Translator.
  • Added support for dual AXI ports for On-Chip Memory II RAM/ROM.
21.3
  • Added support for new IP core in Intel® Quartus® Prime: On-Chip Memory II (RAM or ROM).
  • Added Nios® V Processor support except for the following IP cores:
    • SDRAM Controller Core
    • Tri-State SDRAM Core
    • Compact Flash Core
    • EPCS Serial Flash Controller Core
    • 16207 LCD Controller Core
    • Scatter-Gather DMA Controller Core
    • Video Sync Generator and Pixel Converter Cores
    • Avalon® -ST Test Pattern Generator and Checker Cores
    • Avalon® -MM DDR Memory Half Rate Bridge Core
    • Modular ADC Core
    • Modular Dual ADC Core
    • Intel® FPGA Avalon® Mutex Core
    • Vectored Interrupt Controller Core
20.4
  • No change.
20.3
  • No change.
20.2
  • Added a new parameter for eSPI to LPC Bridge Core.
20.1
  • Added support for new IP core in Intel® Quartus® Prime: Intel® FPGA MII to RMII Converter Core.
19.4
  • No change.
19.3
  • No change.
19.2
  • No change.
19.1
  • Added support for new IP core in Intel® Quartus® Prime: Intel® FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core.
18.1
  • Added support for new IP core in Intel® Quartus® Prime: eSPI to LPC Bridge IP Core.
18.0
  • Added support for new IP core in Intel® Quartus® Prime: Intel® eSPI Slave IP Core.
  • Added a new parameter for Modular Scatter-Gather DMA Core.
17.1
  • mSGDMA optimizations for Intel® Stratix® 10 devices in Intel® Quartus® Prime Pro Edition software version 17.1.
  • CMSIS support for embedded IP in Intel® Quartus® Prime Pro Edition software version 17.1.
  • EPCQA device support for EPCQ Controller and Generic QSPI Controller IP in Intel® Quartus® Prime Standard Edition software version 17.1.
  • Bug Fix:
    • Intel® Avalon® FIFO IP —Incorrect back pressure behavior during reset state and data loss when FIFO is almost full issue is fixed.
  • Intel FPGA Triple-Speed Ethernet (TSE) iniche driver to support mSGDMA updated.
  • Redundant software example simple_socket_server_rgmii removed
17.0
  • Added new Streaming ( Avalon® -ST) Freeze Bridges for Partial Reconfiguration (PR) support.
  • New improved data performance Serial flash controller II and Generic Quad SPI controller II IP cores.
  • Added Avalon® -ST Freeze Bridges as PR solution IP.
  • All Embedded IP cores now support Intel® Cyclone® 10 device compilation.
  • Bug fixes:
    • I2C Slave to Avalon® -MM Master—MM master write data corruption due to overrun of internal I2C slave RX shifting logic issue fixed
    • Intel FPGA Avalon® FIFO IP —Incorrect back pressure behavior during reset state and data loss when FIFO is almost full issue fixed
    • EPCQ Controller—Incorrect back pressure behavior during reset state issue fixed
  • Generic QSPI Controller IP:
    • Modified to enable support for multiple instances in one Platform Designer design.
    • N25Q016 flash device now supported.
  • Serial Flash Controller IP—EPCS4 flash device is now supported.
  • The following IP cores (from Intel® Quartus® Prime Standard Edition) are not present in the Intel® Quartus® Prime Pro Edition:
    • Intel FPGA Avalon® New SDRAM Controller
    • Intel FPGA SDRAM Tristate Controller
    • Intel FPGA Avalon® EPCS Flash Controller
    • Intel FPGA Avalon® Compact Flash Controller
    • Intel FPGA Avalon® Half Rate Bridge
    • Intel FPGA Avalon® Pixel Converter
    • Intel FPGA Avalon® Video Sync Generator
    • Intel FPGA Avalon® LCD 16207
    • Intel FPGA Avalon® SGDMA
    • Intel FPGA Avalon® DMA
    • Intel FPGA Modular ADC
    • Intel FPGA SM Bus Controller
16.1
  • A new IP core named Avalon® I2C Master has been added to the Platform Designer (Standard) library.
  • The 16550 UART IP has been enhanced to support a user-defined TX FIFO level trigger.
  • Freeze controller and bridges IPs have been added to the IP library.
For more information about the respective IP cores, refer to the Embedded Peripherals IP User Guide.

For information about Nios® V, refer to the Nios® V Processor Intel® FPGA IP Release Notes.

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