3.1. Stratix® 10 Power Management and VID Interface Getting Started

Stratix® 10 Power Management User Guide

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ID 683418

Date 4/07/2025

Version

Public

Document Table of Contents

Document Table of Contents x

1. Stratix® 10 Power Management Overview 2. Stratix® 10 Power Management Architecture and Features 3. Stratix® 10 Power Management and VID Interface Implementation Guide 4. Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Stratix® 10 Power Management User Guide

2. Stratix® 10 Power Management Architecture and Features x

2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Stratix® 10 Devices 2.5. Power Supply Design

2.1. Power Consumption x

2.1.1. Dynamic Power Equation

2.2. Power Reduction Techniques and Features x

2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line

2.2.1. SmartVID Standard Power Devices x

2.2.1.1. SmartVID Feature Implementation in Stratix® 10 Devices 2.2.1.2. SDM Power Manager

2.2.1.2. SDM Power Manager x

2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode

2.3. Power-On Reset Circuitry x

2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry

2.4. Power Sequencing Considerations for Stratix® 10 Devices x

2.4.1. Power-Up Sequence Requirements for Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Stratix® 10 Devices

3. Stratix® 10 Power Management and VID Interface Implementation Guide x

3.1. Stratix® 10 Power Management and VID Interface Getting Started

3.1. Stratix® 10 Power Management and VID Interface Getting Started x

3.1.1. Specifying Parameters and Options

3.1.1. Specifying Parameters and Options x

3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Stratix® 10 Power Management and VID Interface QSF Constraint Guide

1. Stratix® 10 Power Management Overview

2. Stratix® 10 Power Management Architecture and Features

2.1. Power Consumption

2.1.1. Dynamic Power Equation

2.2. Power Reduction Techniques and Features

2.2.1. SmartVID Standard Power Devices

2.2.1.1. SmartVID Feature Implementation in Stratix® 10 Devices

2.2.1.2. SDM Power Manager

2.2.1.2.1. PMBus Master Mode

2.2.1.2.2. PMBus Slave Mode

2.2.2. Power-Screened Devices

2.2.3. Temperature Compensation

2.2.4. DSP and M20K Power Gating

2.2.5. Clock Gating

2.2.6. Power Sense Line

2.3. Power-On Reset Circuitry

2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry

2.4. Power Sequencing Considerations for Stratix® 10 Devices

2.4.1. Power-Up Sequence Requirements for Stratix® 10 Devices

2.4.2. Power-Down Sequence Recommendations and Requirements for Stratix® 10 Devices

2.5. Power Supply Design

3. Stratix® 10 Power Management and VID Interface Implementation Guide

3.1. Stratix® 10 Power Management and VID Interface Getting Started

3.1.1. Specifying Parameters and Options

3.1.1.1. Configuration Pin Parameters

3.1.1.2. Power Management and VID Parameters

3.1.1.3. Stratix® 10 Power Management and VID Interface QSF Constraint Guide

4. Stratix® 10 Power Management User Guide Archives

5. Document Revision History for the Stratix® 10 Power Management User Guide