• The FIM locks after the AFU sends a memory read to invalid address.
• Workaround: Power cycle the system to reinitialize the Intel® PAC with Intel® Arria® 10 GX FPGA and recover from this issue. Refer to the Knowledge Base entry for more information.
• Status: Fix targeted for a future version of the Intel® Acceleration Stack.

• Designs may not function properly when a customer loads an AFU for a second time using fpgaconf.
• Workaround: Power cycle the system to reinitialize the Intel® PAC with Intel® Arria® 10 GX FPGA so that you can use fpgaconf to load another AFU. For more information, refer to the Identifying and Updating the FIM section of the Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA .
• Status: Fix targeted for a future version of the Intel® Acceleration Stack.

• The streaming DMA basic building blocks (BBBs) can access host or FPGA memory, but the driver does not provide any means for accessing FPGA memory.
• Status: This limitation will be fixed in a future version of the driver.

Memory-to-stream DMA does not assert start-of-packet (SOP) at the beginning of a packet transfer.

• The memory-to-stream DMA supports packet transfers but it currently does not assert start-of-packet (SOP) at the beginning of a packet transfer.
• Status: This limitation will be fixed in a future version of the driver.

• When performing a non-deterministic length stream-to-memory transfer, the length argument to the driver is ignored.
• Workaround: To prevent the DMA from overflowing, the host buffer ensures that it is sufficiently sized so that the stream-to-memory DMA receives an end-of-packet (EOP) before overflowing the host buffer.
• Status: This limitation will be fixed in a future version of streaming DMA.