Serial Lite IV Intel Agilex® 7 FPGA IP Design Example User Guide

ID 683391
Date 10/02/2023
Public

3.5. Error Handling

The Serial Lite IV IP detects error conditions and the behaviors in response to these error conditions.

Table 11.  Error Condition BehaviorIn this table, N represents the number of lanes.
Signal Width Location Direction Clock Domain Error Indication
tx_error 5 Top-level signal Output tx_core_clkout Not used.
rx_error

(N*2*2)+3 (PAM4 mode)

(N*2)*3 (NRZ mode)

Top-level signal Output rx_core_clkout

When asserted, indicates an error condition on the RX datapath.

  • [(N*2+2):N+3] = Indicates PCS error for a specific lane.
  • [N+2] = Indicates alignment error. Re-initialize lane alignment if this bit is asserted.
  • [N+1]= Indicates data is forwarded to the user logic when user logic is not ready.
  • [N] = Indicates loss of alignment.
  • [(N-1):0] = Indicates the data contains CRC error.

tx_adaptation_fifo_full

1

Top-level TX DCFIFO signal

Output TX user clock This vector indicates the write domain TX buffer is full and cannot accept data.

rx_adaptation_fifo_full

1

Top-level TX DCFIFO signal

Output TX user clock This vector indicates the write domain RX buffer is full and cannot accept data.

readfull

1

Top-level RX DCFIFO signal

Output RX user clock This vector indicates the read domain buffer is full and cannot accept data.