1.6. External Memory Interfaces Stratix® 10 FPGA IP 18.0

Table 16. v18.0 May 2018
Description	Impact
Verified in the Quartus® Prime software v18.0.	Provides external memory interface IP for DDR3, DDR4, QDR II/II+/II+ Xtreme, QDR-IV, and RLDRAM 3 protocols for Stratix® 10 devices. The tables below summarize speed and feature support.

Table 17. DDR4 EMIF IP Speed and Support Levels for Stratix® 10 GX, SX, MX, and TX Devices
Memory Format	Maximum Rate (Mbps/MHz)			EMIF IP Support Level by Stratix® 10 Device Grades
	-1	-2	-3	GX	SX	MX	TX
UDIMM	2666/1333 (1R)	2400/1200 (1R)	1866/933 (1R)	S C T H	S C T H	S C T H	S C T H
	2400/1200 (2R)	2133/1066 (2R)	1600/800 (2R)	S C T H	S C T H	S C T H	S C T H
	2133/1066 (4R)	1866/933 (4R)	1333/667 (4R)	S C T H	S C T H	S C T H	S C T H
	1866/933 (2R+2R)	1600/800 (2R+2R)	1333/667 (2R+2R)	S C T H	S C T H	S C T H	S C T H
SODIMM	2666/1333 (1R)	2400/1200 (1R)	1866/933 (1R)	S C T H	S C T H	S C T H	S C T H
	2400/1200 (2R)	2133/1066 (2R)	1600/800 (2R)	S C T H	S C T H	S C T H	S C T H
	2133/1066 (4R)	1866/933 (4R)	1333/667 (4R)	S C T H	S C T H	S C T H	S C T H
	1866/933 (2R+2R)	1600/800 (2R+2R)	1333/667 (2R+2R)	S C T H	S C T H	S C T H	S C T H
RDIMM	2666/1333 (1R)	2400/1200 (1R)	1866/933 (1R)	S C T H	S C T H	S C T H	S C T H
	2400/1200 (2R)	2133/1066 (2R)	1600/800 (2R)	S C T H	S C T H	S C T H	S C T H
	2133/1066 (4R)	1866/933 (4R)	1333/667 (4R)	S C T H	S C T H	S C T H	S C T H
	1866/933 (2R+2R)	1600/800 (2R+2R)	1333/667 (2R+2R)	S C T H	S C T H	S C T H	S C T H
LRDIMM	2666/1333 (1R)	2400/1200 (1R)	1866/933 (1R)	S C T H	S C T H	S C T H	S C T H
	2666 / 1333 (2R)	2400/1200 (2R)	1866/933 (2R)	S C T H	S C T H	S C T H	S C T H
	2666 / 1333 (4R)	2400/1200 (4R)	1866/933 (4R)	S C T H	S C T H	S C T H	S C T H
	(2R+2R) - 2D4R configuration is supported for Stratix® 10 EMIF IP DDR4 LRDIMM
Component	2666/1333	2400/1200	1866/933	S C T H	S C T H	S C T H	S C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 18. DDR4 EMIF IP Feature Support for Stratix® 10 GX, SX, MX, and TX Devices
Feature Category	Sub-Category	Supported?	EMIF IP Feature Support Level by Stratix® 10 Device Grades
Feature Category	Sub-Category	Supported?	GX	SX	MX	TX
Interface Width	<=72 with DIMM	Yes	S C T H	S C T H	S C T H	S C T H
Interface Width	<=72 component	Yes	S C T H	S C T H	S C T H	S C T H
Controller	Hard controller	Yes	S C T H	S C T H	S C T H	S C T H
PHY	Hard PHY	Yes	S C T H	S C T H	S C T H	S C T H
PHY	PHY Only	Yes	S C T H	S C T H	S C T H	S C T H
Ping Pong		Yes	S C T H	S C T H	S C T H	S C T H
Periodic OCT	Periodic OCT	No	−	−	−	−
3DS		Yes	S C T H	S C T H	S C T H	S C T H
Design Example		Yes	S C T H	S C T H	S C T H	S C T H
Rate (core)	Quarter	Yes	S C T H	S C T H	S C T H	S C T H
DBI	Read DBI	Yes	S C T H	S C T H	S C T H	S C T H
DBI	Write DBI	Yes	S C T H	S C T H	S C T H	S C T H
Mirroring	Address Mirroring for odd ranks for multi rank DIMM	Yes	S C T H	S C T H	S C T H	S C T H
DM	DM pins	Yes	S C T H	S C T H	S C T H	S C T H
Preamble	Read Preamble settings	2	S C T H	S C T H	S C T H	S C T H
Preamble	Write Preamble settings	1	S C T H	S C T H	S C T H	S C T H
Refresh	Temperature-controlled	No	−	−	−	−
	Fine Granularity	No	−	−	−	−
	Auto self-refresh	No	−	−	−	−
	Self-refresh abort	No	−	−	−	−
ODT	Input buffer during power-down mode	No	−	−	−	−
Controller Features	ECC	Yes	S C T H	S C T H	S C T H	S C T H
	Reordering	Yes	S C T H	S C T H	S C T H	S C T H
	Auto Power Down	Yes	S C T H	S C T H	S C T H	S C T H
	User Refresh	Yes	S C T H	S C T H	S C T H	S C T H
	Auto Precharge	Yes	S C T H	S C T H	S C T H	S C T H
	Command Priority	Yes	S C T H	S C T H	S C T H	S C T H
Calibration	Address/Command calibration	Yes	S C T H	S C T H	S C T H	S C T H
Calibration	Multi-rank calibration	Yes	S C T H	S C T H	S C T H	S C T H
Debug	EMIF Toolkit	Yes	C T H	C T H	C T H	C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 19. DDR3 EMIF IP Speed and Support Levels for Stratix® 10 GX, SX, MX, and TX Devices
Memory Format	Maximum Rate (Mbps/MHz)			EMIF IP Support Level by Stratix® 10 Device Grades
	-1	-2	-3	GX	SX	MX	TX
UDIMM	2133/1066 (1R)	2133/1066 (1R)	1866/933 (1R)	S C T H	S C T H	S C T H	S C T H
	1866/933 (2R)	1866/933 (2R)	1600/800 (2R)	S C T H	S C T H	S C T H	S C T H
	1600/800 (4R)	1600/800 (4R)	1334/667 (4R)	S C T H	S C T H	S C T H	S C T H
	1334/667 (2R+2R)	1334/667 (2R+2R)	1334/667 (2R+2R)	S C T H	S C T H	S C T H	S C T H
SODIMM	2133/1066 (1R)	2133/1066 (1R)	1866/933 (1R)	S C T H	S C T H	S C T H	S C T H
	1866/933 (2R)	1866/933 (2R)	1600/800 (2R)	S C T H	S C T H	S C T H	S C T H
	1600/800 (4R)	1600/800 (4R)	1334/667 (4R)	S C T H	S C T H	S C T H	S C T H
	1334/667 (2R+2R)	1334/667 (2R+2R)	1334/667 (2R+2R)	S C T H	S C T H	S C T H	S C T H
RDIMM	2133/1066 (1R)	2133/1066 (1R)	1866/933 (1R)	S C T H	S C T H	S C T H	S C T H
	1866/933 (2R)	1866/933 (2R)	1600/800 (2R)	S C T H	S C T H	S C T H	S C T H
	1600/800 (4R)	1600/800 (4R)	1334/667 (4R)	S C T H	S C T H	S C T H	S C T H
	1334/667 (2R+2R)	1334/667 (2R+2R)	1334/667 (2R+2R)	S C T H	S C T H	S C T H	S C T H
LRDIMM	LRDIMM memory format is not supported for Stratix® 10 FPGA EMIF IP DDR3
Component	2133/1066	2133/1066	1866/933	−	−	−	−
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 20. DDR3 EMIF IP Feature Support for Stratix® 10 GX, SX, MX, and TX Devices
Feature Category	Sub-Category	Supported?	EMIF IP Feature Support Level by Stratix® 10 Device Grades
Feature Category	Sub-Category	Supported?	GX	SX	MX	TX
Interface Width	<=72 with DIMM	Yes	S C T H	S C T H	S C T H	S C T H
Interface Width	<=72 component	Yes	S C T H	S C T H	S C T H	S C T H
Controller	Hard controller	Yes	S C T H	S C T H	S C T H	S C T H
PHY	Hard PHY	Yes	S C T H	S C T H	S C T H	S C T H
PHY	PHY Only	Yes	S C T H	S C T H	S C T H	S C T H
Ping Pong		Yes	S C T H	S C T H	S C T H	S C T H
Design Example		Yes	S C T H	S C T H	S C T H	S C T H
Rate (core)	Quarter	Yes	S C T H	S C T H	S C T H	S C T H
	Half	Yes	S C T H	S C T H	S C T H	S C T H
	Full	Yes	S C T H	S C T H	S C T H	S C T H
Mirroring	Address Mirroring for odd ranks for multi rank DIMM	Yes	S C T H	S C T H	S C T H	S C T H
DM	DM pin	Yes	S C T H	S C T H	S C T H	S C T H
Controller Features	ECC	Yes	S C T H	S C T H	S C T H	S C T H
	Reordering	Yes	S C T H	S C T H	S C T H	S C T H
	Auto Power Down	Yes	S C T H	S C T H	S C T H	S C T H
	User Refresh	Yes	S C T H	S C T H	S C T H	S C T H
	Auto Precharge	Yes	S C T H	S C T H	S C T H	S C T H
	Command Priority	Yes	S C T H	S C T H	S C T H	S C T H
Calibration	Address/Command calibration	Yes	S C T H	S C T H	S C T H	S C T H
Calibration	Multirank calibration	Yes	S C T H	S C T H	S C T H	S C T H
Debug	EMIF Toolkit	Yes	C T H	C T H	C T H	C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 21. QDR-IV and QDR II/II+/Xtreme EMIF IP Speed and Support Levels for Stratix® 10 GX, SX, MX, and TX Devices
Protocol	Maximum Rate (Mbps/MHz)			EMIF IP Support Level by Stratix® 10 Device Grades
	-1	-2	-3	GX	SX	MX	TX
QDR-IV	2133/1066	2133/1066	1866/933	S C T H	S C T H	S C T H	S C T H
QDR II+ Xtreme BL=4	1266/633	1100/550	1000/500	S C T H	S C T H	S C T H	S C T H
QDR II+ Xtreme BL=2	900/450	800/400	800/400	S C T H	S C T H	S C T H	S C T H
QDR II+ BL=4	1100/550	1000/500	900/450	S C T H	S C T H	S C T H	S C T H
QDR II+ BL=2	800/400	700/350	600/300	S C T H	S C T H	S C T H	S C T H
QDR II BL=4	700/350	700/350	700/350	S C T H	S C T H	S C T H	S C T H
QDR II BL=2	600/300	600/300	600/300	S C T H	S C T H	S C T H	S C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 22. QDR-IV EMIF IP Feature Support for Stratix® 10 GX, SX, MX, and TX Devices
Feature Category	Sub-Category	Supported?	EMIF IP Feature Support Level by Stratix® 10 Device Grades
Feature Category	Sub-Category	Supported?	GX	SX	MX	TX
Memory Format	Component	Yes	S C T H	S C T H	S C T H	S C T H
Memory Type	XP	Yes	S C T H	S C T H	S C T H	S C T H
Interface Width	<=72 with DIMM	Yes	S C T H	S C T H	S C T H	S C T H
Controller	Soft controller	Yes	S C T H	S C T H	S C T H	S C T H
PHY	Hard PHY	Yes	S C T H	S C T H	S C T H	S C T H
Design Example		Yes	S C T H	S C T H	S C T H	S C T H
Rate (core)	Quarter	Yes	S C T H	S C T H	S C T H	S C T H
Debug	EMIF Toolkit	Yes	C T H	C T H	C T H	C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 23. QDR II/II+/Xtreme EMIF IP Feature Support for Stratix® 10 GX, SX, MX, and TX Devices
Feature Category	Sub-Category	Supported?	EMIF IP Feature Support Level by Stratix® 10 Device Grades
Feature Category	Sub-Category	Supported?	GX	SX	MX	TX
Memory Format	Component	Yes	S C T H	S C T H	S C T H	S C T H
Interface Width	<=72 with DIMM	Yes	S C T H	S C T H	S C T H	S C T H
PHY	Hard PHY	Yes	S C T H	S C T H	S C T H	S C T H
Design Example		Yes	S C T H	S C T H	S C T H	S C T H
Rate (core)	Half	Yes	S C T H	S C T H	S C T H	S C T H
Rate (core)	Full	Yes	S C T H	S C T H	S C T H	S C T H
Debug	EMIF Toolkit	Yes	S C T H	S C T H	S C T H	S C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 24. RLDRAM 3 EMIF IP Speed and Support Levels for Stratix® 10 GX, SX, MX, and TX Devices
Format	Maximum Rate (Mbps/MHz)			EMIF IP Support Level by Stratix® 10 Device Grades
	-1	-2	-3	GX	SX	MX	TX
Component	2400/1200	2133/1066	1866/933	S C T H	S C T H	S C T H	S C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 25. RLDRAM 3 EMIF IP Feature Support for Stratix® 10 GX, SX, MX, and TX Devices
Feature Category	Sub-Category	Supported?	EMIF IP Feature Support Level by Stratix® 10 Device Grades
Feature Category	Sub-Category	Supported?	GX	SX	MX	TX
Interface Width	<=72 with DIMM	Yes	S C T H	S C T H	S C T H	S C T H
Controller		No	−	−	−	−
PHY	Hard PHY only	Yes	S C T H	S C T H	S C T H	S C T H
Design Example		Yes	S C T H	S C T H	S C T H	S C T H
Rate (core)	Quarter	Yes	S C T H	S C T H	S C T H	S C T H
DM	DM pins	Yes	S C T H	S C T H	S C T H	S C T H
Debug	EMIF Toolkit	Yes	C T H	C T H	C T H	C T H
Support level key: S = simulation support C = compilation support T = timing support H = hardware support

Table 26. EMIF IP Debug Support
		Supported?
On-chip debug	On-chip debug (with soft Nios® )	Yes
EMIF Debug Toolkit	Calibration margin	Yes
	Traffic Generator 2.0	No
	2D Eye	No
	Driver margining	Yes
	Efficiency monitor	No
	ODT Tuning	Yes
	RDBI + Driver margining	Yes
	Rank support	Yes

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External Memory Interfaces Stratix® 10 FPGA IP Core Release Notes

1.6. External Memory Interfaces Stratix® 10 FPGA IP 18.0