Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 10/02/2023
Document Table of Contents

4.4.3. Avalon® Memory-Mapped Host Interfaces and Load-Store Units

When your component uses one or more Avalon® Memory-Mapped (MM) Host interfaces, the Intel® HLS Compiler inserts load-store units (LSUs) in the datapath between the interface and the rest of your component datapath. The type of LSU inserted depends on the inferred memory access pattern and other memory attributes.

The Intel® HLS Compiler also tries to minimize the number of LSUs created by coalescing multiple load/store operations into wider load/store operations. Multiple LSUs can share a memory interface.

Typically, the Intel® HLS Compiler creates burst-coalesced LSUs for variable-latency MM Host interfaces and pipelined LSUs for fixed-latency MM Host interfaces.

For details about the types of the LSUs and when the Intel® HLS Compiler typically instantiates them, see Load-Store Unit Types and Memory-Access Coalescing and Load-Store Units.

If your design contains one or more variable-latency Avalon® MM Host interfaces (for example, if you interface with off-chip memory), you can control the LSU type to improve the performance and resource utilization of your design.

LSUs are also used when your component interacts with on-chip memories described in Component Memories (Memory Attributes).

Use the high-level design reports to determine what types of LSUs your component has, and then you can apply these LSU controls as needed to achieve the component performance that you want.

Table 14.   Intel® HLS Compiler Pro Edition Load-Store Unit Control Summary


ihc::lsu The underlying LSU class template object
ihc::style Specifies the type of load-store unit.
ihc::static_coalescing Explicitly allows or prevents static coalescing of a load/store operation with other load/store operations.
load Loads data from memory into the LSU.
store Stores data from the LSU into memory.