Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 6/26/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.5. Agent Interfaces

The Intel® HLS Compiler can implement two different types of Avalon® Memory Mapped ( Avalon® MM) agent interface for your component parameters: a control-and-status register (CSR) agent interface and an agent memory interface.
In general, use the CSR agent interface to pass scalar values to your component and use the agent memory interface to pass large arrays to and from your component.

For details about the Avalon® MM Agent interfaces, see "Avalon Memory-Mapped Interfaces in Avalon Interface Specifications.

Table 15.  Types of Agent Interfaces
Agent Type Associated Agent Interface Read/Write Behavior Synchronization Read Latency Controlling Interface Data Width
Register The component CSR agent. The component cannot update these registers from the datapath, so you can read back only data that you wrote in. Synchronized with the component start signal. Fixed value of 1. Always 64 bits
Memory (M20K/MLAB) Dedicated agent interface on the component.

The component reads from this memory and updates it as it runs.

Updates from the component datapath are visible in memory.

Reads and writes to agent memories from outside of the component should occur only when your component is not executing.

You might experience undefined component behavior if outside agent memory accesses occur when your component is executing. The undefined behavior can occur even if an agent memory access is to a memory address that the component does not access.

Fixed value that is dependent on the component memory access pattern and any attributes or pragmas that you set.

See the Function Viewer report in the High-Level Design Report (report.html) for the read latency of a specific agent memory argument.

The data width is a multiple of the agent data type, where the multiple is determined by coalescing the internal accesses.