## Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 10/04/2021
Public

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## 7.3. Component Pipelining Control (hls_disable_component_pipelining Attribute)

If running concurrent invocations of your component does not improve throughput, or if you do not intend to invoke your component repeatedly, avoid extra FPGA area utilization by using the hls_disable_component_pipelining component attribute.

When you specify the hls_disable_component_pipelining, the Intel® HLS Compiler generates a simpler, serialized datapath for your component.

You apply the attribute as shown in the following example:
#include "HLS/hls.h"

hls_disable_component_pipelining
component void baz ( /* arguments */ ){
// component code
}

You can also disable pipelining the datapath of a loop in your component with the disable_loop_pipelining pragma. For more information about this pragma see Loop Pipelining Control (disable_loop_pipelining Pragma).

Review the Loop Analysis report in the High-Level Design Reports (report.html) to see component invocations and loops with pipelining disabled:

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