Serial Lite III Streaming Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 5/23/2024
Document Table of Contents

1. Quick Start Guide

Updated for:
Intel® Quartus® Prime Design Suite 24.1
IP Version 20.1.0
The Serial Lite III Streaming Intel® FPGA IP provides the capability of generating design examples for selected configurations.

The Serial Lite III Streaming Intel® FPGA IP offers eight preset settings for Stratix® 10 H-tile and L-tile devices in both simplex and duplex modes and Stratix® 10 E-tile devices in duplex mode.

  • Standard Clocking Mode 6x12.5G
  • Standard Clocking Mode 6x17.4G
  • Standard Clocking Mode 2x25G
  • Standard Clocking Mode 4x28G
  • Advanced Clocking Mode 6x12.5G
  • Advanced Clocking Mode 6x17.4G
  • Advanced Clocking Mode 2x25G
  • Advanced Clocking Mode 4x28G
Figure 1. Development Stages for the Design Example