Fixed-Point IP Cores (ALTERA_FIXED-POINT_FUNCTIONS) User Guide

ID 683339
Date 10/15/2021
Public

3. Fixed-Point IP Cores Parameters and Signals

Each IP core allows you to specify the data width, which is the total number of bits that make up the fixed-point number. Specifying a sign uses one of the bits.
Table 2.  Performance Tab ParametersEach IP core allows you to view resource usage in the IP Parameter Editor GUI. The parallel add, modular multiply, divide, integer divide and square root IPs allow you to adjust your implementation based on your chosen frequency or latency target. The parallel add, modular multiply, divide, and square root IPs allow you to designate some of the bits to represent a fixed-point fraction.
Parameter Description
Goal Select Frequency, Latency, or Combined performance target
Target Enter the frequency in MHz at which you expect this function to run. The IP core determines the amount of pipelining from this frequency and the target device family.
Check Performance Click Check Performance to view the resource usage.

Parallel Add

This IP calculates the sum of the inputs.

Turn on Wide adder architecture (under the Options tab) for an architecture optimized for very wide bit-widths. This architecture reduces both resource utilization and latency. The wide adder architecture requires that all inputs share the same format.

Table 3.  Parallel Add Parameters
Parameter Description
Input data widths
Input name Autogenerated name of this input to the generated IP core.
Width The width of this fixed-point data interface.
Fraction The number of fraction bits in this fixed-point data interface.
Sign The signedness of this fixed-point data interface.
+ Click + to add more inputs; click - to remove inputs.
Output data widths
Automatic output type Tturn on automatic output type to allow the IP core to determine the output format based on the input and operation.
Width
Fraction
Sign
Options
Disable adder word growth The addition and or subtraction logic in the IP core normally allows for word growth. To disable word growth turn on this option.
Generate an enable port Turn on if you want the function to have an enable signal.
Wide adder architecture Turn on for wide operand bit-widths (hundred to thousands of bits) when all inputs share the same formats.
Wide adder ripple-carry chunk size This option allows you to set the maximum primitive adder size that the wide adder architecture uses. Intel recommends to set this value to be a multiple of the LAB ripple-carry adder chain size: 20, 40, 60 etc. A value of 40 typically provides a good balance between resource utilization and performance. Specify a value of 20 if you require a very high frequency.
Table 4.  Parallel Add Signals
Signal Direction Description
clk Input Clock.
reset Input Reset.
a0 Input Input a0.
a1 Input Input a1.
result Output The parallel add result.

Multiply

This IP multiplies the two inputs. The IP provides architectures optimized for multiplying wide operands (tens to thousands of bits), if you turn on Wide multiplier architecture under the Options tab.

Table 5.  Multiply Parameters
Parameter Description
Complex Data You can configure a multiplier to operate on complex valued inputs and optionally use the Karatsuba method for multiplication of complex numbers. Complex valued inputs and outputs are concatenated real and imaginary values of the data format you specify. The real part occupies the lower bits of the input or output bus. Complex multiplication requires four multiplications and two additions.
Karatsuba complex multiplicaiton

The Karatsuba option reduces the number of multipliers to three, increases the number of adders to five.

Input data widths
Width The width of this fixed-point data interface
Fraction The number of fraction bits in this fixed-point data interface
Sign The signedness of this fixed-point data interface
Output data widths
Automatic output type Turn on automatic output type to allow the IP core to determine the output format based on the input and operation.
Width
Fraction
Sign
Options
Generate an enable port Turn on if you want the function to have an enable signal.
Wide multiplier architecture

Use when multiplying wide unsigned operands having the same widths. Allows you to telect the wide multiplier architecture for IP including the classical schoolbook algorithm and several variations of the Karatsuba algorithm.

Architecture

This drop-down list allows selecting one of four advanced architecture options:

  • Schoolbook algorithm performs a classical decomposition and uses the best DSP-block modes depending on the frequency target.
  • Flat Karatsuba implements a multiplier using a non-recursive Karatsuba algorithm; the sweet-spots are multiples of 26 (52, 78, 104, 130, 156 etc).
  • Recursive Karatsuba decomposes recursively the large multiplier into smaller ones, until the leaf multiplier size becomes smaller or equal to 26 bits.
  • Hybrid Karatsuba is similar to the Recursive Karatsuba, but the leaf-level nodes are implemented using Flat Karatsuba. Use the Flat-Karatsuba threshold value parameter to select the maximum leaf-level size. Multipliers less than or equal to this size are implemented using Flat Karatsuba.
Flat-Karatsuba threshold value This advanced option is available for Hybrid Karatsuba. The threshold value indicates that all multipliers resulting from the recursive Karatsuba decomposition that have sizes smaller or equal to this value are implemented using Flat Karatsuba. Ideal values for this field include multiples of 26 (one less than the DSP Block multiplier size in 27x27 configuration). Select the value of 130 when implementing multipliers of sizes 256, 512, 1,024, 2,048 etc.

If the IP core cannot represent the product of the inputs in the output format you chose, the result is undefined.

Table 6.  Multiply Signals
Signal Direction Description
clk Input Clock.
reset Input Reset.
a Input Input a.
b Input Input b.
result Output The multiply result.

Modular Multiply

This IP implements a modular multiplier using Barrett’s algorithm. The IP inputs A, B and the modulus M and returns AB % M. A, B and M share the same bit-width and they are unsigned. For each set of inputs A, B and M, the IP also requires you to provide R, which is an approximation to the reciprocal of M. R is to be provided on width+1 bits and is computed as R=saturate(floor(4^width/M)). The IP requires that M is in the interval [2^(width-1), (2^width)-1], and therefore requires that the most significant bit of M is 1.

The IP also allows you to instantiate this modular multiplier for a fixed modulus value. You can input the modulus value using the provided text field. You can select the base used for expressing the modulus value. The modulus value must also be in the interval [2^(width-1), (2^width)-1].

For example, when width=8 the allowed modulus values are [128, 255].

Table 7.  Modular Multiply Parameters
Parameter Description
Width Width of multiplier inputs A and B, the modulus M and the result. The reciprocal of the modulus R is one bit wider.
Constant Modulus Turn on to fix the value of the modulus.
Modulus Value Setting the value of the modulus when you turn on Constant Modulus. The modulus value must be in the interval [2^(width-1), 2^(width)-1].
Base Available when you turn on Constant Modulus. The value in Modulus Value is interpreted in the base indicated by this selection. The four bases are: binary, octal, decimal, and hexadecimal. For example, a modulus value of 1000 and a base of binary corresponds to the decimal value 8.

Divide

This IP core produces the result of the first input, numerator, divided by the second input, denominator. The Divide IP core has a fixed-point output. You can control the number of significant bits in the output by adjusting the output data format. If you reduce the number of bits in the output, the divider uses fewer resources.

The LSB in the divider's output is faithfully rounded. Use the Integer Divide IP core to obtain true equivalence to a truncating CPU integer divider. The faithfully rounded result has an accuracy of one unit in the last place, where one unit in the last place is the weight of the LSB. For example, if the output format has zero fraction bits, the weight of the LSB is 2^0=1. If the result is 3.2, the IP core can either return 3 or 4, where both results are equally valid.

Table 8.  Divide Parameters
Parameter Description
Input data widths
Width The width of this fixed-point data interface
Fraction The number of fraction bits in this fixed-point data interface. Divide IP core only.
Sign The signedness of this fixed-point data interface
Output data widths
Automatic output type Turn on to allow the IP core to determine the output format based on the input and operation.
Width The width of this fixed-point data interface.
Fraction The number of fraction bits in this fixed-point data interface. Divide IP core only.
Options
Generate an enable port Turn on if you want the function to have an enable signal.
Table 9.  Divide Signals
Signal Direction Description
clk Input Clock.
reset Input Reset.
numerator Input Numerator.
denominator Input Denominator.
result Output The division result.

Square Root

The output is faithfully rounded. The faithfully rounded result has an accuracy of one unit in the last place, where one unit in the last place is the weight of the LSB. For example, if the output format has zero fraction bits, the weight of the LSB is 2^0=1. If the result is 3.2, the IP core can either return 3 or 4, where both results are equally valid.

Table 10.  Square Root Parameters
Parameter Description
Input data widths
Width The width of this fixed-point data interface
Fraction The number of fraction bits in this fixed-point data interface
Sign The signedness of this fixed-point data interface
Output data widths
Automatic output type Turn on to allow the IP core to determine the output format based on the input and operation.
Width The width of this fixed-point data interface.
Fraction The number of fraction bits in this fixed-point data interface.
Sign The signedness of this fixed-point data interface.
Options
Generate an enable port Turn on if you want the function to have an enable signal.
Table 11.  Square Root Signals
Signal Direction Description
clk Input Clock.
reset Input Reset.
radical Input
result Output The square root result.

Integer Divide

This IP core produces the result of the first input, numerator, divided by the second input, denominator. The Divide IP core has a fixed-point output. You can control the number of significant bits in the output by adjusting the output data format. If you reduce the number of bits in the output, the divider uses fewer resources.

The Integer Divide IP core offers true equivalence to a truncating CPU integer divider.

Table 12.  Integer Divide Parameters
Parameter Description
Input data widths
Width The width of this fixed-point data interface
Sign The signedness of this fixed-point data interface
Output data widths
Automatic output type Turn on to allow the IP core to determine the output format based on the input and operation.
Width The width of this fixed-point data interface.
Options
Generate an enable port Turn on if you want the function to have an enable signal.
Table 13.  Integer Divide Signals
Signal Direction Description
clk Input Clock.
reset Input Reset.
numerator Input Numerator.
denominator Input Denominator.
result Output The division result.

Simple Counter

This IP core maintains a counter and produces the counter value each cycle.The value of the counter increments by the positive step value every cycle for which the enable input is high.

The counter limit is its rollover value. The IP core sizes a counter to accommodate a value one less than the limit you specify. For example, a limit of 65,536 specifies a 16-bit counter. If the start value is 0 and the step value is 1, the counter rolls over from 65,535 to 0.

The limit must be equal to start plus an integer multiple of step.

Table 14.  Simple Counter Parameters
Parameter Description
Start value

The counter initialises to this value on reset and when incrementing a step reaches the Limit. The Start value must be greater than zero.

Step

The increment that the IP core applies on each cycle when the counter's enable input is high. The simple counter's step must be positive. Step must be greater than zero.

Limit

The counter counts up to one step away from this value. If adding the step value to the counter reaches the limit, the counter returns to Start value. Limit must be greater than or equal to Start.

Table 15.  Simple Counter Signals
Signal Direction Description
clk Input Clock.
rst Input Reset.
en Input Enable.
value Output

Loadable Counter

This IP core maintains a counter and produces the counter value each cycle.T

You configure the counter with start value, step and limit values. You specify an initial configuration at setup time using the IP GUI. The counter always uses this configuration on reset. The counter allows changing configurations at runtime. To set new values at runtime, change the corresponding input signals (start, step and limit) and hold the sload signal high for one cycle.

The initial reset initializes the counter to the setup start value. Then counter value gets incremented by the step value in every cycle for which the enable signal is high.

You can specify the counter width and its sign. These values determine the range of the counter [minValue, maxValue]. If the counter type is w-bit unsigned, minValue=0 and maxValue=(2^width) – 1. If the counter type is w-bit signed, minValue=-2^(width-1) and maxValue=(2^(width-1))-1.

For positive limit values, and when enable is high, the next value of the counter is computed as (value + step) % limit. % denotes the remainder operation.

For example, for a 5-bit signed counter, which is loaded with start value=7, step=3 and limit=13, the counter values are 10, 0, 3, 6, 9, 12, 2, 5, 8.

When the limit is negative, the next counter value is minValue + ((value + step) % (maxValue+1)). As the next counter value exceeds the set limit, the next counter value is computed as the difference between this value and the limit.

For example, for a 5-bit signed counter, which is loaded with start value=13, step=3 and limit=-10 the next counter value is -16 + ((13+3)%16) = -16. The value after that is -16+3=-13. The next value -13+3=-10 reaches the limit, and the next counter value is set to -10-(-10)=0. The next values are 3, 6, 9, 12, 15. The next counter value after 15 is (-16 + ((15+3)%16))=-14. The value after is -11. The next value is (-11+3)-(-10)=2.

The loadable counter requires that step is a positive value. The IP requires the initial start value and limit are also positive values, and that their difference be a multiple of the step size.

Table 16.  Loadable Counter Parameters
Parameter Description
Start value

The counter initializes to this value on reset and when incrementing a step reaches the Limit.

Step

The increment that the IP core applies on each cycle when the counter's enable input is high.

Limit

The counter counts up to one step away from this value. If adding the step value to the counter reaches the limit, the counter returns to Start value.

Output data widths
Width The width of this fixed-point data interface. The width of the counter and its Start, Step, and Limit inputs.
Sign The signedness of this fixed-point data interface. Although the interface may be signed, the IP only supports the unsigned range of values for start and step.
Table 17.  Loadable Counter Signals
Signal Direction Description
clk Input Clock.
rst Input Reset.
en Input Enable.
sload Input When sload is high, the IP replaces the counter's internal start, step, and limit values by values from the corresponding input signals. The counter requires that you provide positive values for start and step.
step Input
start Input
limit Input
value Output  

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