SDI Audio Intel FPGA IP User Guide

Download PDF
ID 683333
Date 10/05/2020
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon-ST Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed Parameters 4.2. SDI Audio Extract Parameters 4.3. SDI Audio Clocked Audio Input Parameters 4.4. SDI Audio Clocked Audio Output Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed Signals 5.2. SDI Audio Extract Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

1.1. Release Information

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

The IP version (X.Y.Z) number may change from one Intel Quartus Prime software version to another. A change in:

  • X indicates a major revision of the IP. If you update your Intel Quartus Prime software, you must regenerate the IP.
  • Y indicates the IP includes new features. Regenerate your IP to include these new features.
  • Z indicates the IP includes minor changes. Regenerate your IP to include these changes.
Table 1.  SDI Audio Intel® FPGA IP Cores Current Release Information

Item

Description

IP Version

19.1.0
Intel® Quartus® Prime Version

19.2

Release Date

July 2019

Ordering Code

IP-SDI-II

Device Family

Intel® Quartus® Prime Pro Edition: Intel® Arria® 10 GX, Intel® Arria® 10 GT, and Intel® Arria® 10 SX FPGA device families.

Level Two Title