HDMI Cyclone® 10 GX FGPA IP Design Example User Guide

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ID 683309
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices 2. HDMI Design Example 3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. Design Limitation 1.7. HDMI Intel® FPGA IP Design Example Parameters
2. HDMI Design Example x
2.1. HDMI RX-TX Retransmit Design Block Diagram 2.2. Design Components 2.3. Dynamic Range and Mastering (HDR) InfoFrame Insertion and Filtering 2.4. Clocking Scheme 2.5. Interface Signals 2.6. Design RTL Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Cyclone® 10 GX Devices
2. HDMI Design Example
3. HDMI Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for HDMI Cyclone® 10 GX FPGA IP Design Example User Guide

2.9. Upgrading Your Design

Table 25.  HDMI Design Example Compatibility with Previous Quartus® Prime Pro Edition Software Version
Design Example Variant Ability to Upgrade to Quartus® Prime Pro Edition 24.1
HDMI 2.0 Design Example No
For any non-compatible design examples, you need to do the following:
  1. Generate a new design example in the current Quartus® Prime Pro Edition software version using the same configurations of your existing design.
  2. Compare the whole design example directory with the design example generated using the previous Quartus® Prime Pro Edition software version. Port over the changes found.
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