ModelSim* - Intel® FPGA Edition Simulation Quick-Start: Intel® Quartus® Prime Pro Edition

ID 683305
Date 12/30/2019

1.4. Modify the Simulator Setup Script

Modify the generated simulator setup script to enable specific commands that simulate the IP cores in the project.
  1. In a text editor, open the /PLL_RAM/mentor/msim_setup.tcl file.
  2. Create a new text file with the name and save it in the /PLL_RAM/mentor/ directory.
  3. In the msim_setup.tcl file, copy the section of code enclosed within the TOP-LEVEL TEMPLATE – BEGIN and TOP-LEVEL TEMPLATE – END comments, and then paste this code into the new file.
  4. In the file, delete the single pound (#) characters preceding the following highlighted lines to enable compilation commands:
    Figure 3. Uncomment Highlighted Simulation Commands in the Script
  5. Replace the following lines in the script:
    Table 1.  Specify Values in the Script
    Replace this Line With this Line
    set QSYS_SIMDIR <script generation output directory> ../
    vlog <compilation options> <design and testbench files>
    vlog -vlog01compat -work work ../PLL_RAM.v
    vlog -vlog01compat -work work ../UP_COUNTER_IP/UP_COUNTER_IP.v
    vlog -vlog01compat -work work ../DOWN_COUNTER_IP/DOWN_COUNTER_IP.v
    vlog -vlog01compat -work work ../ClockPLL/ClockPLL.v
    vlog -vlog01compat -work work ../RAMhub/RAMhub.v
    vlog -vlog01compat -work work ../testbench_1.v
    set TOP_LEVEL_NAME <simulation top> set TOP_LEVEL_NAME tb
    run -a
    add wave *
    view structure
    view signals
    run -all
  6. Save the /PLL_RAM/mentor/ file. The following figure shows the file after revisions are complete:
    Figure 4. Completed Top-Level IP Simulation Setup Script