Intel® Quartus® Prime Pro Edition Settings File Reference Manual

ID 683296
Date 4/03/2023
Public

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Document Table of Contents

TIMING_ANALYZER_DO_REPORT_CDC_VIEWER

Directs the Timing Analyzer to report a table of all clock domain transfers for each analysis.

Type

Boolean

Device Support

  • This setting can be used in projects targeting any Intel FPGA device family.

Notes

None

Syntax

set_global_assignment -name TIMING_ANALYZER_DO_REPORT_CDC_VIEWER <value>

Default Value

Off