Mailbox Client Intel® FPGA IP User Guide

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ID 683290
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. Mailbox Client Intel FPGA IP User Guide 2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions
1. Mailbox Client Intel FPGA IP User Guide x
1.1. Device Family Support 1.2. Parameters 1.3. Mailbox Client Intel® FPGA IP Core Interface Signals 1.4. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface 1.5. Commands and Responses 1.6. Specifying the Command and Response FIFO Depths 1.7. Enabling Cryptographic Services 1.8. Using the Mailbox Client Intel FPGA IP 1.9. Mailbox Client Intel FPGA IP Core Use Case Examples 1.10. Nios® II and Nios® V Processors HAL Driver 1.11. Mailbox Client Intel FPGA IP User Guide Archives 1.12. Document Revision History for the Mailbox Client Intel® FPGA IP User Guide
1.3. Mailbox Client Intel® FPGA IP Core Interface Signals x
1.3.1. Clock and Reset Interfaces 1.3.2. Avalon® Memory-Mapped Interface 1.3.3. AXI Manager Interface
1.4. Mailbox Client Intel FPGA IP Avalon® Memory-Mapped Interface x
1.4.1. Interrupt Enable Register 1.4.2. Interrupt Status Register 1.4.3. Timer Registers
1.5. Commands and Responses x
1.5.1. Operation Commands 1.5.2. Error Code Responses 1.5.3. Error Code Recovery
1.10. Nios® II and Nios® V Processors HAL Driver x
1.10.1. Mailbox Client HAL API 1.10.2. LibRSU HAL API
1.10.1. Mailbox Client HAL API x
1.10.1.1. Mailbox Client Driver API
1.10.2. LibRSU HAL API x
1.10.2.1. Configuration Parameter 1.10.2.2. Error Codes 1.10.2.3. Using LibRSU HAL API without Valid SPT or CPB 1.10.2.4. Data Type 1.10.2.5. Functions 1.10.2.6. RSU Client API
1. Mailbox Client Intel FPGA IP User Guide
2. Appendix: CONFIG_STATUS and RSU_STATUS Error Code Descriptions

1.4.1. Interrupt Enable Register

Use the Interrupt Enable register to enable or disable interrupts.
Note: These enable bits do not prevent the value of interrupt status bit from showing up in ISR, they only prevent the interrupt status bit from causing interrupt output assertion via IRQ signal.
Table 6.  Interrupt Enable Register
Bit Fields Access Default Value Description
31:8 Reserved
9 EN_RD_RSP_FIFO_WHEN_EMPTY R/W 0x0 The enable interrupt bit for read response FIFO when empty detection.
  • 1: Enable the read response FIFO when empty detection interrupt bit.
  • 0: Disable the read response FIFO when empty detection interrupt bit.
8 EN_WR_CMD_FIFO_WHEN_FULL R/W 0x0 The enable interrupt bit for write command FIFO when full detection.
  • 1: Enable the write command FIFO when full interrupt bit
  • 0: Disable the write command FIFO when full interrupt bit
7 EN_CRYPTO_ERROR_RECOVERY_PROGRESS 3 R/W 0x0 The enable interrupt bit for crypto service error recovery progress status.
  • 1: Enable the crypto service error recovery progress interrupt
  • 0: Disable the crypto service error recovery progress interrupt
6 EN_CRYPTO_MEMORY_TIMEOUT 3 R/W 0x0 The enable interrupt bit for the crypto service client-side memory timeout.
  • 1: Enable the crypto service client-side memory timeout interrupt
  • 0: Disable the crypto service client-side memory timeout interrupt
5 EN_BACKPRESSURE_TIMEOUT R/W 0x0 The enable interrupt bit for SDM backpressure timeout.
  • 1: Enable the SDM backpressure timeout interrupt
  • 0: Disable the SDM backpressure timeout interrupt
4 EN_EOP_TIMEOUT R/W 0x0 The enable interrupt bit for EN_EOP_TIMEOUT.
  • 1: Enable the EOP timeout interrupt
  • 0: disable the EOP timeout interrupt
3 EN_COMMAND_INVALID R/W 0x0 The enable interrupt bit for COMMAND_INVALID.
  • 1: Enable the command invalid interrupt
  • 0: Disable the command invalid interrupt
2 Reserved — — Reserved.
1 EN_CMD_FIFO_NOT_FULL R/W 0x0 The enable for the command FIFO full interrupt.
  • 1: Enable the FIFO full interrupt
  • 0: Disable the FIFO full interrupt
0 EN_DATA_VALID R/W 0x0 The enable for the data valid interrupt.
  • 1: Enable the data valid interrupt
  • 0: Disable the data valid interrupt
3 The crypto service feature is only available for Intel Agilex® 7 devices.
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