F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 8/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

3.8. Analog Parameters

Through this tab, you can configure FHT and FGT PMAs settings. Altera recommends the following FHT and FGT PMAs settings for Agilex™ 7 I-Series Transceiver-SoC development kit:
Figure 19. FHT PMA SettingsThe recommended FHT PMA settings are shown below.
  • FHT TX
    • Enable FHT TX P&N Invert: Enabled
    • Select FHT TX Termination: TXTERM_OFFSET_M1(96.8 Ohms)
  • FHT RX
    • Enable FHT RX P&N Invert: Enabled
    • Select FHT RX Termination: RXTERM_OFFSET_P0(90 Ohms)
  • FHT PLL
    • Select FHT external AC Cap: EXTERNAL_AC_CAP_DISABLE
  • FHT TX EQ
    • Post-Cursor 2, 0.25 step size: -2.0
    • Post-Cursor 1, 0.5 step size: -2.0
    • Main-Cursor, 0.5 step size: 18.0
    • Pre-Cursor 1, 0.5 step size: -4.0
Figure 20. FGT PMA SettingsThe recommended FGT PMA settings are shown below.
Note: When the design configuration is PAM4 modulation with more than 8 lanes, set the FGT TXEQ Pre Tap 1 as 5.
Note: Depending on the data rate, use the following setting:
  1. For NRZ data rate of more than or equal to 23 Gbps, select VSR_MODE_LOW_LOSS.
  2. For NRZ data rate of less than 23 Gbps, select VSR_MODE_DISABLE.
  3. For PAM4 with number of lanes less than or equal to 8, select VSR_MODE_LOW_LOSS.
  4. For PAM4 with number of lanes more than 8, select VSR_MODE_HIGH_LOSS.
When the NRZ data rate is less than 7 Gbps, Altera recommends to set the following parameters to use 0s.
  • RXEQ VGA Gain
  • RXEQ High Frequency Boost
  • RXEQ DFE Data Tap1
Figure 21. RXEQ Settings
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