F-Tile CPRI PHY Intel® FPGA IP User Guide

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ID 683284
Date 2/03/2023
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile CPRI PHY Intel® FPGA IP Core 2. Getting Started 3. IP Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide
1. About the F-Tile CPRI PHY Intel® FPGA IP Core x
1.1. Supported Features 1.2. Overview 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Resource Utilization 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. IP Core Testbenches
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Reset Logic 4.2. Latency Measurement
4.2. Latency Measurement x
4.2.1. Deterministic Latency 4.2.2. Calculation for 64b/66b Datapath
5. Interface Signals x
5.1. Clock Signals 5.2. Reset Signals 5.3. TX MII Interface (64b/66b) 5.4. RX MII Interface (64b/66b) 5.5. Status Interface for 64b/66b Line Rate 5.6. TX Interface (8b/10b) 5.7. RX Interface (8b/10b) 5.8. Status Interface for 8b/10b Line Rate 5.9. Serial Interface 5.10. CPRI PHY Reconfiguration Interface 5.11. Datapath Avalon Memory-Mapped Interface 5.12. PMA Avalon Memory-Mapped Interface
5.1. Clock Signals x
5.1.1. Required Clock Frequencies
1. About the F-Tile CPRI PHY Intel® FPGA IP Core
2. Getting Started
3. IP Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile CPRI PHY Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

8. Document Revision History for the F-Tile CPRI PHY Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.02.03 22.4 4.1.0

Deterministic Latency: Instances of signal ethlphy_wa changed to eth_wa occurring in the table Delay Equations for 10G/12G/24G without RS-FEC Variants

2022.09.26 22.3 4.0.0
  • Added support for new reference clock (122.88 MHz).
    • Updated the following sections:
      • Supported Features
      • IP Parameter Settings
      • Required Clock Frequencies
  • Corrected register names in section: Calculation for 64b/66b Datapath.
2022.06.21 22.2 3.3.0 Added the hardware design example support for:
  • Intel® Agilex™ I-Series FPGA Development Kit
  • Intel® Agilex™ I-Series Transceiver-SoC Development Kit
2022.03.28 22.1 3.2.0
  • Removed support for ModelSim* SE simulator.
  • Added a new parameter: Enable CDR Clock Output.
  • Updated the Required Clock Frequencies section.
2021.12.13 21.4 3.1.0
  • Added support for Xcelium* simulator.
  • Updated the Resource Utilization.
  • Added a new parameter: Enable Debug Endpoint for Datapath and PMA Avalon Memory-Mapped Interface.
2021.10.04 21.3 3.0.0
  • Added support for the following line rates:
    • 1.228 Gbps
    • 3.072 Gbps
    • 6.144 Gbps
  • Updated the following sections with new line rate information:
    • Supported Features
    • Resource Utilization
    • IP Parameter Settings
  • Updated the deterministic latency equations in section: Deterministic Latency.
  • Updated the address range for the IP Registers.
  • Added support for the following simulators:
    • Siemens* EDA QuestaSim* simulator
    • Questa* Intel® FPGA Edition simulator
2021.06.21 21.2 2.0.0 Initial release.
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