F-Tile CPRI PHY Altera® FPGA IP Design Example User Guide
ID
683281
Date
3/30/2025
Public
1.1. Hardware and Software Requirements
1.2. Generating the Design Example
1.3. Directory Structure
1.4. Simulating the Design Example
1.5. Compiling the Compilation-Only Project
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Hardware Design Example
1.8. Transceiver Toolkit
1.1. Hardware and Software Requirements
To test the example design, use the following hardware and software:
- Quartus® Prime Pro Edition software
- System console available with the Quartus® Prime Pro Edition software
- A supported simulator:
- Synopsys* VCS*
- Synopsys* VCS* MX
- Siemens* EDA QuestaSim*
- Questa* Intel® FPGA Edition
- Cadence* Xcelium*
- Agilex™ 7 I-Series Transceiver-SoC Development Kit