F-Tile CPRI PHY Altera® FPGA IP Design Example User Guide
ID
683281
Date
3/30/2025
Public
1.1. Hardware and Software Requirements
1.2. Generating the Design Example
1.3. Directory Structure
1.4. Simulating the Design Example
1.5. Compiling the Compilation-Only Project
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Hardware Design Example
1.8. Transceiver Toolkit
2.5. Interface Signals
Signal | Direction | Description |
---|---|---|
ref_clk100MHz | Input | Input clock for CSR access on all the reconfiguration interfaces. Drive at 100 MHz. |
i_clk_ref[0] | Input | Reference clock for System PLL. Drive at 156.25 MHz. |
i_clk_ref[1] | Input | Transceiver reference clock. Drive at:
|
i_rx_serial[n] | Input | Transceiver PHY input serial data. |
o_tx_serial[n] | Output | Transceiver PHY output serial data. |