F-Tile CPRI PHY Altera® FPGA IP Design Example User Guide

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ID 683281
Date 3/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. F-Tile CPRI PHY Altera® FPGA IP Design Example User Guide Archives 4. Document Revision History for the F-Tile CPRI PHY Altera® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design Example 1.3. Directory Structure 1.4. Simulating the Design Example 1.5. Compiling the Compilation-Only Project 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example 1.8. Transceiver Toolkit
1.2. Generating the Design Example x
1.2.1. Design Example Parameters Example Design Tab Analog Parameters Tab 1.2.2. Analog Parameters for F-Tile IPs
1.4. Simulating the Design Example x
1.4.1. Simulating the Design Example Testbench 1.4.2. Simulating the Design Example Testbench Simplified Model
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. F-Tile CPRI IP Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL
1. Quick Start Guide
2. Design Example Description
3. F-Tile CPRI PHY Altera® FPGA IP Design Example User Guide Archives
4. Document Revision History for the F-Tile CPRI PHY Altera® FPGA IP Design Example User Guide

1.2.1. Design Example Parameters

Describes the F-Tile CPRI PHY IP Design Example Example Design and Analog Parameters tabs

Example Design Tab

If you select Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit for Target Development Kit, it only supports OSC_CLK_1_125MHZ for Device initialization clock. If you configure analog parameters other than the default and recommended values (Table 1), you see warnings to recommend you set to the default values.

Figure 3. Target Development Kit in the Example Design Tab
Figure 4. Warnings

Analog Parameters Tab

For all parameters in the Analog Parameters tab, refer to the Analog Parameters for F-Tile IPs.

When the CPRI rate is 6.1440G and below, the GUI has three extra analog parameters to configure:
  • RXEQ VGA Gain
  • RXEQ High Frequency Boost
  • RXEQ DFE Data Tap1
Figure 5. For CPRI Rates 9.8304G and Above
Figure 6. For CPRI Rates 6.1440G and Below
Table 1.  Default and Recommended Analog Parameter Values

The table shows default and recommended analog parameters values:
Parameter Value
FGT TXEQ Post Tap 1, 1.0 step size 0
FGT TXEQ Main Tap 1.0 step size 35
FGT TXEQ Pre Tap 1, 1.0 step size 5
FGT TXEQ Pre Tap 2, 1.0 step size 0
FGT RX Onchip Termination RX_ONCHIP_TERMINATION_R_2 (100 ohms)
Enable FGT RX AC Couple ENABLE
Enable FGT VSR mode
  • VSR_MODE_LOW_LOSS (for CPRI rate 24Gbps only)
  • VSR_MODE_DISABLE (shown error if it’s not selected for CPRI rate below 24Gbps)
RXEQ VGA Gain 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ High Frequency Boost 0 (Required only when CPRI rate is 6.1440Gbps and below)
RXEQ DFE Data Tap1 0 (Required only when CPRI rate is 6.1440Gbps and below)

For RXEQ VGA Gain, RXEQ High Frequency Boost and RXEQ DFE Data Tap1 registers for manual tuning, refer to the F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map FGT tab.

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