25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

Download PDF
ID 683252
Date 6/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. 25G Ethernet Intel® FPGA IP Quick Start Guide 2. 10G/25G Ethernet Single-Channel Design Example for Stratix® 10 Devices 3. 25G Ethernet Single-Channel Design Example for Stratix® 10 Devices 4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices 5. 25G Ethernet Intel® FPGA IP Design Example References 6. 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives 7. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide
1. 25G Ethernet Intel® FPGA IP Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware 1.5. Changing Target Device in Hardware Design Example 1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.3. Simulating the 25G Ethernet Intel® FPGA IP Design Example Testbench x
1.3.1. Procedure
1.4. Compiling and Configuring the Design Example in Hardware x
1.4.1. Procedure
1.5. Changing Target Device in Hardware Design Example x
1.5.1. Procedure
1.6. Testing the 25G Ethernet Intel® FPGA IP Design in Hardware x
1.6.1. Procedure
2. 10G/25G Ethernet Single-Channel Design Example for Stratix® 10 Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 2.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
2.6. Hardware Testing x
2.6.1. Test Procedure—Design Example Without the IEEE 1588v2 Feature 2.6.2. Test Procedure—Design Example with the IEEE 1588v2 Feature
3. 25G Ethernet Single-Channel Design Example for Stratix® 10 Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Compilation 3.6. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Design Example Without the IEEE 1588v2 Feature 3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature
3.6. Hardware Testing x
3.6.1. Test Procedure—Design Example With and Without the IEEE 1588v2 Feature
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices x
4.1. Features 4.2. Hardware and Software Requirements 4.3. Functional Description 4.4. Simulation 4.5. Compilation 4.6. Hardware Testing
4.3. Functional Description x
4.3.1. Design Components
4.4. Simulation x
4.4.1. Testbench 4.4.2. Simulation Design Example Components 4.4.3. Test Case
4.6. Hardware Testing x
4.6.1. Test Procedure
5. 25G Ethernet Intel® FPGA IP Design Example References x
5.1. Design Example Interface Signals 5.2. Design Example Registers 5.3. Using Transceiver Toolkit on H-Tile Production Device
1. 25G Ethernet Intel® FPGA IP Quick Start Guide
2. 10G/25G Ethernet Single-Channel Design Example for Stratix® 10 Devices
3. 25G Ethernet Single-Channel Design Example for Stratix® 10 Devices
4. 25G Ethernet Multi-Channel Design Example for Intel Stratix 10 Devices
5. 25G Ethernet Intel® FPGA IP Design Example References
6. 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide Archives
7. Document Revision History for the 25G Ethernet Stratix® 10 Intel® FPGA IP Design Example User Guide

3.4.4. Test Case—Design Example with the IEEE 1588v2 Feature

Note: For 25G Ethernet single-channel design example with IEEE 1588v2 feature simulation testbench, refer to Functional Description.

The simulation test case performs the following actions:

  1. Instantiates , ATX PLL, and IO PLL (sampling PLL).
  2. Waits for RX clock and PHY status signal to settle.
  3. Prints PHY status.
  4. Checks for 10 valid data.
  5. Analyzes the results. The successful testbench displays "Testbench complete." when the PTP delay and offset data are within the threshold values.

The following sample output illustrates a successful simulation test run:

# 
# Waiting for RX alignment...
# iatpg_pipeline_global_en is set
# iatpg_pipeline_global_en is set
# RX deskew locked.
# RX lane aligmnent locked.
# 
# Sending packets...
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064457
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000064bb4
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000fffffffff8a2
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000634fb
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063f3b
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063a1a
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x00000000000000000006445a
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000063e95
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000648d5
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000000
# Offset within tolerence range.
# 
# 
# Delay (sec[95:48],ns[47:16],fns[15:0]): 0x0000000000000000000643b5
# Offset(sec[95:48],ns[47:16],fns[15:0]): 0x000000000000000000000520
# Offset within tolerence range.
# 
# 
# 
# Finished sending packets.
# 
# **
# ** Testbench complete.
# **
Figure 19. Sample Simulation Output for Design Example with the IEEE 1588v2 Feature (Part 1 of 2)
Figure 20. Sample Simulation Output for Design Example with the IEEE 1588v2 Feature (Part 2 of 2)
Level Two Title