O-RAN Intel® FPGA IP User Guide

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ID 683238
Date 3/01/2023
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Document Table of Contents
Document Table of Contents x
1. About the O-RAN Intel® FPGA IP 2. Getting Started with the O-RAN Intel® FPGA IP 3. O-RAN IP Functional Description 4. O-RAN IP Registers 5. O-RAN Intel FPGA IP User Guide Archive 6. Document Revision History for the O-RAN Intel® FPGA IP User Guide
1. About the O-RAN Intel® FPGA IP x
1.1. O-RAN Intel® FPGA IP Features 1.2. O-RAN Intel® FPGA IP Device Family Support 1.3. Release Information for the O-RAN Intel® FPGA IP 1.4. O-RAN Intel® FPGA IP Performance and Resource Utilization
2. Getting Started with the O-RAN Intel® FPGA IP x
2.1. Obtaining, Installing, and Licensing the O-RAN IP 2.2. Parameterizing the O-RAN IP 2.3. Generated IP File Structure
2.2. Parameterizing the O-RAN IP x
2.2.1. O-RAN IP Parameters
3. O-RAN IP Functional Description x
3.1. O-RAN IP Signals 3.2. O-RAN Intel® FPGA IP Error Handling 3.3. O-RAN Reset Transactions 3.4. O-RAN IP Streaming Mode 3.5. O-RAN IP Performance Counters 3.6. O-RAN IP Transmission and Reception Window Threshold 3.7. O-RAN IP Fragmentation
1. About the O-RAN Intel® FPGA IP
2. Getting Started with the O-RAN Intel® FPGA IP
3. O-RAN IP Functional Description
4. O-RAN IP Registers
5. O-RAN Intel FPGA IP User Guide Archive
6. Document Revision History for the O-RAN Intel® FPGA IP User Guide

3.3. O-RAN Reset Transactions

The IP has five external reset ports.

The five external reset ports are:

  • rst_tx_n. Resets the O-RAN IP in the transmission direction. Resets the common header mapper, transmission window monitor and C and U-plane mapper.
  • rst_rx_n. Resets the O-RAN IP in the receiver direction. Resets the common header demapper, reception window monitor and C- and U-plane demapper.
  • rst_csr_n. Resets the O-RAN IP control and status registers. Assert to reset the IP.
  • tx_lanes_stable. Resets the O-RAN IP in the transmission direction when deasserted. Assertion indicates the transmitter clock is stable and O-RAN IP transmitter path is ready to come out from reset. Connect this reset to the Ethernet MAC output or tie to 1.
  • rx_pcs_ready. Resets the O-RAN IP in the receiver direction when deasserted. Assertion indicates the receiver clock is stable and O-RAN IP receiver path is ready to come out from reset. Connect this reset to the Ethernet MAC output or tie to 1.
Figure 15. O-RAN IP Resets

Intel expects the three external reset ports to assert together to fully reset the O-RAN IP. You can deassert the three reset ports together or deassert rst_csr_n, then reset_tx_n, and reset_rx_n to reset CSR, transmitter path, receiver path, respectively.

The reset flow occurs before the O-RAN IP starts. Deassert the Avalon Streaming application interface ready signals to indicate IP is not ready to receive any transaction.

Alternatively, you can trigger a reset after reconfiguring O-RAN IP during run time.

Figure 16. Reset DeassertionThe timing diagram shows tx_lanes_stable and rx_pcs_ready tied to 1 and both the O-RAN and Ethernet IP sharing the same CSR, transmit, and receive reset ports. On deasserting a reset,the O-RAN IP deasserts the internal IP reset and sends a request when the eCPRI IP asserts the Avalon Streaming ready signal.
Figure 17. Reset DeassertionThe timing diagram shows the tx_lanes_stable and rx_pcs_ready connected to the Ethernet MAC output interface and both the O-RAN and Ethernet IP sharing the same CSR, transmit and receive reset ports. On deasserting a reset, the Ethernet MAC cycles through the reset deassertion flow and then asserts tx_lanes_stable and rx_pcs_ready. When the O-RAN IP sees tx_lanes_stable and rx_pcs_ready assertions, the ORAN IP deasserts the internal IP reset.
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